PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28890
Change subject: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions. ......................................................................
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions.
-cnl PCH-H has 12 GPIO groups which are grouped under 5 gpio community.
-Add gpio pin definitions for CNP-H and related changes.
-Add gpio device name, host software owenership reg offset for CNP-H.
BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verified power management, IO device functionalities works fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/gpio.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/pmc.h 6 files changed, 545 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28890/1
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 8a990b3..bcf67f9 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +20,11 @@
Device (GPIO) { +#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) + Name (_HID, "INT3450") +#else Name (_HID, "INT34BB") +#endif Name (_UID, 0) Name (_DDN, "GPIO Controller")
@@ -83,6 +87,7 @@ */ Method (GADD, 1, NotSerialized) { +#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11))) { @@ -116,6 +121,35 @@ Store (PCRB (Local0), Local2) Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 16))) +#else + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3*/ + If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_K0, Local1) + } + /* GPIO Community 4*/ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 16))) +#endif }
/* diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 0befba0..ca3b7ec 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2015-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +31,7 @@ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, }; - +#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) static const struct pad_group cnl_community0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */ INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */ @@ -145,6 +145,118 @@ .num_groups = ARRAY_SIZE(cnl_community4_groups), } }; +#else +static const struct pad_group cnl_community0_groups[] = { + INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */ + INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */ +}; + +static const struct pad_group cnl_community1_groups[] = { + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ + INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */ + INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */ +}; + +static const struct pad_group cnl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ +}; + +static const struct pad_group cnl_community3_groups[] = { + INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/ + INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */ + INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */ +}; + +static const struct pad_group cnl_community4_groups[] = { + INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */ + INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */ +}; + +static const struct pad_community cnl_communities[] = { + { /* GPP A, B */ + .port = PID_GPIOCOM0, + .first_pad = GPP_A0, + .last_pad = GPP_B23, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_AB", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map_com0, + .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = cnl_community0_groups, + .num_groups = ARRAY_SIZE(cnl_community0_groups), + }, { /* GPP C, D, G */ + .port = PID_GPIOCOM1, + .first_pad = GPP_C0, + .last_pad = GPP_G7, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CDG", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community1_groups, + .num_groups = ARRAY_SIZE(cnl_community1_groups), + }, { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD11, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community2_groups, + .num_groups = ARRAY_SIZE(cnl_community2_groups), + }, { /* GPP K, H, E, F */ + .port = PID_GPIOCOM3, + .first_pad = GPP_K0, + .last_pad = GPP_F23, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_KHEF", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community3_groups, + .num_groups = ARRAY_SIZE(cnl_community3_groups), + }, { /* GPP I, J */ + .port = PID_GPIOCOM4, + .first_pad = GPP_I0, + .last_pad = GPP_J11, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_IJ", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community4_groups, + .num_groups = ARRAY_SIZE(cnl_community4_groups), + } +}; +#endif
const struct pad_community *soc_gpio_get_community(size_t *num_communities) { @@ -163,6 +275,11 @@ { PMC_GPP_F, GPP_F }, { PMC_GPP_G, GPP_G }, { PMC_GPP_H, GPP_H }, +#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) + { PMC_GPP_I, GPP_I }, + { PMC_GPP_J, GPP_J }, + { PMC_GPP_K, GPP_K }, +#endif { PMC_GPD, GPD }, }; *num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 2d9f3d7..a2b6f5e 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,10 @@
#include <soc/gpio_defs.h> #include <intelblocks/gpio.h> - +#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) +#define CROS_GPIO_DEVICE_NAME "INT3450:00" +#else #define CROS_GPIO_DEVICE_NAME "INT34BB:00" +#endif
#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 716f59d..6f9c03a 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. + * Copyright 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -240,12 +240,92 @@ #define GPP_H21_IRQ 0x5d #define GPP_H22_IRQ 0x5e #define GPP_H23_IRQ 0x5f - +#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) +/* Group I */ +#define GPP_I0_IRQ 0x18 +#define GPP_I1_IRQ 0x19 +#define GPP_I2_IRQ 0x1a +#define GPP_I3_IRQ 0x1b +#define GPP_I4_IRQ 0x1c +#define GPP_I5_IRQ 0x1d +#define GPP_I6_IRQ 0x1e +#define GPP_I7_IRQ 0x1f +#define GPP_I8_IRQ 0x20 +#define GPP_I9_IRQ 0x21 +#define GPP_I10_IRQ 0x22 +#define GPP_I11_IRQ 0x23 +#define GPP_I12_IRQ 0x24 +#define GPP_I13_IRQ 0x25 +#define GPP_I14_IRQ 0x26 +#define GPP_I15_IRQ 0x27 +#define GPP_I16_IRQ 0x28 +#define GPP_I17_IRQ 0x29 +#define GPP_I18_IRQ 0x2a +#define GPP_I19_IRQ 0x2b +#define GPP_I20_IRQ 0x2c +#define GPP_I21_IRQ 0x2d +#define GPP_I22_IRQ 0x2e +#define GPP_I23_IRQ 0x2f +/* Group J */ +#define GPP_J0_IRQ 0x30 +#define GPP_J1_IRQ 0x31 +#define GPP_J2_IRQ 0x32 +#define GPP_J3_IRQ 0x33 +#define GPP_J4_IRQ 0x34 +#define GPP_J5_IRQ 0x35 +#define GPP_J6_IRQ 0x36 +#define GPP_J7_IRQ 0x37 +#define GPP_J8_IRQ 0x38 +#define GPP_J9_IRQ 0x39 +#define GPP_J10_IRQ 0x3a +#define GPP_J11_IRQ 0x3b +#define GPP_J12_IRQ 0x3c +#define GPP_J13_IRQ 0x3d +#define GPP_J14_IRQ 0x3e +#define GPP_J15_IRQ 0x3f +#define GPP_J16_IRQ 0x40 +#define GPP_J17_IRQ 0x41 +#define GPP_J18_IRQ 0x42 +#define GPP_J19_IRQ 0x43 +#define GPP_J20_IRQ 0x44 +#define GPP_J21_IRQ 0x45 +#define GPP_J22_IRQ 0x46 +#define GPP_J23_IRQ 0x47 +/* Group K */ +#define GPP_K0_IRQ 0x48 +#define GPP_K1_IRQ 0x49 +#define GPP_K2_IRQ 0x4a +#define GPP_K3_IRQ 0x4b +#define GPP_K4_IRQ 0x4c +#define GPP_K5_IRQ 0x4d +#define GPP_K6_IRQ 0x4e +#define GPP_K7_IRQ 0x4f +#define GPP_K8_IRQ 0x50 +#define GPP_K9_IRQ 0x51 +#define GPP_K10_IRQ 0x52 +#define GPP_K11_IRQ 0x53 +#define GPP_K12_IRQ 0x54 +#define GPP_K13_IRQ 0x55 +#define GPP_K14_IRQ 0x56 +#define GPP_K15_IRQ 0x57 +#define GPP_K16_IRQ 0x58 +#define GPP_K17_IRQ 0x59 +#define GPP_K18_IRQ 0x5a +#define GPP_K19_IRQ 0x5b +#define GPP_K20_IRQ 0x5c +#define GPP_K21_IRQ 0x5d +#define GPP_K22_IRQ 0x5e +#define GPP_K23_IRQ 0x5f +#endif /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 +#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) +#define HOSTSW_OWN_REG_0 0xc0 +#else #define HOSTSW_OWN_REG_0 0xb0 +#endif #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index a1ce8c4..db6ce57 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. - * Copyright 2017 Intel Corp. + * Copyright 2017-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ * The GPIO groups are accessed through register blocks called * communities. */ +#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) #define GPP_A 0 #define GPP_B 1 #define GPP_G 2 @@ -352,4 +353,290 @@ #define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)
#define TOTAL_PADS 275 + +#else + +#define GPP_A 0 +#define GPP_B 1 +#define GPP_C 2 +#define GPP_D 3 +#define GPP_G 4 +#define GPP_K 5 +#define GPP_H 6 +#define GPP_E 7 +#define GPP_F 8 +#define GPP_I 9 +#define GPP_J 0xA +#define GPD 0xC +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 + +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 + +#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 48 +#define GPP_C1 49 +#define GPP_C2 50 +#define GPP_C3 51 +#define GPP_C4 52 +#define GPP_C5 53 +#define GPP_C6 54 +#define GPP_C7 55 +#define GPP_C8 56 +#define GPP_C9 57 +#define GPP_C10 58 +#define GPP_C11 59 +#define GPP_C12 60 +#define GPP_C13 61 +#define GPP_C14 62 +#define GPP_C15 63 +#define GPP_C16 64 +#define GPP_C17 65 +#define GPP_C18 66 +#define GPP_C19 67 +#define GPP_C20 68 +#define GPP_C21 69 +#define GPP_C22 70 +#define GPP_C23 71 + +/* Group D */ +#define GPP_D0 72 +#define GPP_D1 73 +#define GPP_D2 74 +#define GPP_D3 75 +#define GPP_D4 76 +#define GPP_D5 77 +#define GPP_D6 78 +#define GPP_D7 79 +#define GPP_D8 80 +#define GPP_D9 81 +#define GPP_D10 82 +#define GPP_D11 83 +#define GPP_D12 84 +#define GPP_D13 85 +#define GPP_D14 86 +#define GPP_D15 87 +#define GPP_D16 88 +#define GPP_D17 89 +#define GPP_D18 90 +#define GPP_D19 91 +#define GPP_D20 92 +#define GPP_D21 93 +#define GPP_D22 94 +#define GPP_D23 95 + +/* Group G */ +#define GPP_G0 96 +#define GPP_G1 97 +#define GPP_G2 98 +#define GPP_G3 99 +#define GPP_G4 100 +#define GPP_G5 101 +#define GPP_G6 102 +#define GPP_G7 103 + +#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1) + +/* Group K */ +#define GPP_K0 104 +#define GPP_K1 105 +#define GPP_K2 106 +#define GPP_K3 107 +#define GPP_K4 108 +#define GPP_K5 109 +#define GPP_K6 110 +#define GPP_K7 111 +#define GPP_K8 112 +#define GPP_K9 113 +#define GPP_K10 114 +#define GPP_K11 115 +#define GPP_K12 116 +#define GPP_K13 117 +#define GPP_K14 118 +#define GPP_K15 119 +#define GPP_K16 120 +#define GPP_K17 121 +#define GPP_K18 122 +#define GPP_K19 123 +#define GPP_K20 124 +#define GPP_K21 125 +#define GPP_K22 126 +#define GPP_K23 127 + +/* Group H */ +#define GPP_H0 128 +#define GPP_H1 129 +#define GPP_H2 130 +#define GPP_H3 131 +#define GPP_H4 132 +#define GPP_H5 133 +#define GPP_H6 134 +#define GPP_H7 135 +#define GPP_H8 136 +#define GPP_H9 137 +#define GPP_H10 138 +#define GPP_H11 139 +#define GPP_H12 140 +#define GPP_H13 141 +#define GPP_H14 142 +#define GPP_H15 143 +#define GPP_H16 144 +#define GPP_H17 145 +#define GPP_H18 146 +#define GPP_H19 147 +#define GPP_H20 148 +#define GPP_H21 149 +#define GPP_H22 150 +#define GPP_H23 151 + +/* Group E */ +#define GPP_E0 152 +#define GPP_E1 153 +#define GPP_E2 154 +#define GPP_E3 155 +#define GPP_E4 156 +#define GPP_E5 157 +#define GPP_E6 158 +#define GPP_E7 159 +#define GPP_E8 160 +#define GPP_E9 161 +#define GPP_E10 162 +#define GPP_E11 163 +#define GPP_E12 164 + +/* Group F */ +#define GPP_F0 165 +#define GPP_F1 166 +#define GPP_F2 167 +#define GPP_F3 168 +#define GPP_F4 169 +#define GPP_F5 170 +#define GPP_F6 171 +#define GPP_F7 172 +#define GPP_F8 173 +#define GPP_F9 174 +#define GPP_F10 175 +#define GPP_F11 176 +#define GPP_F12 177 +#define GPP_F13 178 +#define GPP_F14 179 +#define GPP_F15 180 +#define GPP_F16 181 +#define GPP_F17 182 +#define GPP_F18 183 +#define GPP_F19 184 +#define GPP_F20 185 +#define GPP_F21 186 +#define GPP_F22 187 +#define GPP_F23 188 + +#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1) + +/* Group I */ +#define GPP_I0 189 +#define GPP_I1 190 +#define GPP_I2 191 +#define GPP_I3 192 +#define GPP_I4 193 +#define GPP_I5 194 +#define GPP_I6 195 +#define GPP_I7 196 +#define GPP_I8 197 +#define GPP_I9 198 +#define GPP_I10 199 +#define GPP_I11 200 +#define GPP_I12 201 +#define GPP_I13 202 +#define GPP_I14 203 + +/* Group J */ +#define GPP_J0 204 +#define GPP_J1 205 +#define GPP_J2 206 +#define GPP_J3 207 +#define GPP_J4 208 +#define GPP_J5 209 +#define GPP_J6 210 +#define GPP_J7 211 +#define GPP_J8 212 +#define GPP_J9 213 +#define GPP_J10 214 +#define GPP_J11 215 + +#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1) + +/* Group GPD */ +#define GPD0 216 +#define GPD1 217 +#define GPD2 218 +#define GPD3 219 +#define GPD4 220 +#define GPD5 221 +#define GPD6 222 +#define GPD7 223 +#define GPD8 224 +#define GPD9 225 +#define GPD10 226 +#define GPD11 227 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#define TOTAL_PADS (GPD11 + 1) +#endif #endif diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 90cd370..faa36d4 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -116,6 +116,20 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H) +#define PMC_GPP_A 0 +#define PMC_GPP_B 1 +#define PMC_GPP_C 2 +#define PMC_GPP_D 3 +#define PMC_GPP_E 7 +#define PMC_GPP_F 8 +#define PMC_GPP_G 4 +#define PMC_GPP_H 6 +#define PMC_GPP_I 9 +#define PMC_GPP_J 0xA +#define PMC_GPP_K 5 +#define PMC_GPD 0xC +#else #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0xD @@ -125,6 +139,7 @@ #define PMC_GPP_G 0x2 #define PMC_GPP_H 0x6 #define PMC_GPD 0xA +#endif
#define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5)
-
PraveenX Hodagatta Pranesh (Code Review)