HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6383
-gerrit
commit 961f25f373e05296c3a11cac71fcdadaa534c58f Author: Elyes HAOUAS ehaouas@noos.fr Date: Sun Jul 27 17:12:45 2014 +0200
src/cpu: fixe small texts
Change-Id: I06dd453afbc5067152b064e8818d5fddde572d89 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 8 ++++---- src/cpu/dmp/vortex86ex/biosdata_ex.inc | 4 ++-- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/haswell/haswell_init.c | 2 +- src/cpu/intel/haswell/smmrelocate.c | 2 +- src/cpu/intel/hyperthreading/intel_sibling.c | 10 +++++----- src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 4 ++-- src/cpu/intel/model_f3x/model_f3x_init.c | 4 ++-- src/cpu/intel/model_f4x/model_f4x_init.c | 4 ++-- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 4 ++-- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 22 +++++++++++----------- src/cpu/x86/mp_init.c | 6 +++--- src/cpu/x86/sipi_vector.S | 4 ++-- src/cpu/x86/smm/smm_module_loader.c | 8 ++++---- src/cpu/x86/smm/smm_stub.S | 8 ++++---- src/cpu/x86/smm/smmrelocate.S | 4 ++-- 51 files changed, 97 insertions(+), 97 deletions(-)
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 6fbfd1a..05ec628 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -60,7 +60,7 @@ static void model_10_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 635bd81..3c2b7ce 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -66,7 +66,7 @@ static void model_12_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 60a88c7..25fa701 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -86,7 +86,7 @@ static void model_14_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index a755e1c..9f711c3 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -71,7 +71,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 64c78af..7163aa8 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -85,7 +85,7 @@ static void model_15_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index ef31f96..e5efbbd 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -83,7 +83,7 @@ static void model_16_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c index 8fbf507..9c211c9 100644 --- a/src/cpu/amd/geode_gx1/geode_gx1_init.c +++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c @@ -81,7 +81,7 @@ static void geode_gx1_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..b6bad4d 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic();
vsm_end_post_smi(); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index ebadec7..c3d2572 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -81,7 +81,7 @@ static void disablememoryreadorder(void) wrmsr(MC_CF8F_DATA, msr); }
-/* For cpu version C3. Should be the only released version */ +/* For CPU version C3. Should be the only released version */ void cpubug(void) { pcideadlock(); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index cd931a4..cdd72b5 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -44,7 +44,7 @@ static void geode_lx_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic();
// do VSA late init diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..eb188a9 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -179,7 +179,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state) continue; if ((readback & 0x3f) == state || (readback & 0x3f) == F10_APSTATE_RESET) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..10d3b53 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -66,7 +66,7 @@ static void model_10xxx_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index e68611b..464e5b3 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -402,7 +402,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) 0) continue; if (((readback >> 24) & 0xff) == apicid) - break; /* it is this cpu turn */ + break; /* it is this CPU turn */ }
if (loop > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..f846421 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -144,7 +144,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state) continue; if ((readback & 0xff) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { @@ -271,7 +271,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait - lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started
if (apicid != bsp_apicid) { u32 timeout = 1; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..55547b8 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -234,15 +234,15 @@ static void init_ecc_memory(unsigned node_id)
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); if (!f1_dev) { - die("Cannot find cpu function 1\n"); + die("Cannot find CPU function 1\n"); } f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2)); if (!f2_dev) { - die("Cannot find cpu function 2\n"); + die("Cannot find CPU function 2\n"); } f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3)); if (!f3_dev) { - die("Cannot find cpu function 3\n"); + die("Cannot find CPU function 3\n"); }
/* See if we scrubbing should be enabled */ @@ -486,7 +486,7 @@ static void model_fxx_init(device_t dev) /* Set the processor name string */ init_processor_name();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc index 4a2478e..86ef03a 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc @@ -28,8 +28,8 @@ DDR3 CPU/DRAM/PCI B6 B7 BB BC BD BF 200/200/33 30 03 0F 02 8F 07 300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable +300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable 300/300/100 48 03 23 02 7F 07 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing 400/200/100 60 43 23 02 4F 07 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 0392f69..8464876 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other CPU files are included. # # Therefore: ONLY include Makefile.inc from socket directories!
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 433636d..0819132 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -38,7 +38,7 @@ static void ep80579_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index d0b2d3d..157d564 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -315,7 +315,7 @@ static void intel_cores_init(device_t cpu) struct device_path cpu_path; device_t new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -324,7 +324,7 @@ static void intel_cores_init(device_t cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -334,7 +334,7 @@ static void intel_cores_init(device_t cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -368,7 +368,7 @@ static void model_206ax_init(device_t cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 043ba3a..3ee72e1 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -740,7 +740,7 @@ static void haswell_init(device_t cpu) /* Clear out pending MCEs */ configure_mca();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 56d435c..606ac51 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -184,7 +184,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) return; }
- printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 16d8959..5f205d0 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -8,7 +8,7 @@ #include <assert.h>
#if CONFIG_PARALLEL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init +#error Intel hyper-threading requires serialized CPU init #endif
static int first_time = 1; @@ -63,7 +63,7 @@ void intel_sibling_init(device_t cpu) cpu->path.apic.apic_id, siblings);
- /* See if I am a sibling cpu */ + /* See if I am a sibling CPU */ if (cpu->path.apic.apic_id & (siblings -1)) { if (disable_siblings) { cpu->enabled = 0; @@ -71,16 +71,16 @@ void intel_sibling_init(device_t cpu) return; }
- /* I am the primary cpu start up my siblings */ + /* I am the primary CPU start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; device_t new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
- /* Allocate new cpu device structure iff sibling CPU + /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ new = alloc_find_dev(cpu->bus, &cpu_path); diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 1feb504..1cab11b 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,5 @@ ################################################################################ -## One small file with the awesome super-power of updating the cpu microcode +## One small file with the awesome super-power of updating the CPU microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 4779a51..e2fa564 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -326,7 +326,7 @@ static void model_1067x_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Initialize the APIC timer */ @@ -351,7 +351,7 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(tm2, quad);
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..4e89734 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -128,7 +128,7 @@ static void model_106cx_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -142,7 +142,7 @@ static void model_106cx_init(device_t cpu)
/* TODO: PIC thermal sensor control */
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index c310a67..3501d4d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -368,13 +368,13 @@ static void intel_cores_init(device_t cpu) struct device_path cpu_path; device_t new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + (i % threads_per_core) + ((i / threads_per_core) << 2);
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -384,7 +384,7 @@ static void intel_cores_init(device_t cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -421,7 +421,7 @@ static void model_2065x_init(device_t cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4e56414..b8aec4b 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -502,7 +502,7 @@ static void intel_cores_init(device_t cpu) struct device_path cpu_path; device_t new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -511,7 +511,7 @@ static void intel_cores_init(device_t cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -521,7 +521,7 @@ static void intel_cores_init(device_t cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -557,7 +557,7 @@ static void model_206ax_init(device_t cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index a9f1811..3af0e9c 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -40,7 +40,7 @@ static void model_65x_init(device_t dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 467d3db..df3be0b 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -44,7 +44,7 @@ static void model_67x_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index d1b4463..adf808e 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -49,7 +49,7 @@ static void model_68x_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 4339274..8e0c034 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -18,7 +18,7 @@ static void model_69x_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index d166bfa..650da15 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -49,7 +49,7 @@ static void model_6bx_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 18c2fa4..f9ae4fc 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -18,7 +18,7 @@ static void model_6dx_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..4e7b6e2 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -159,7 +159,7 @@ static void model_6ex_init(device_t cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -174,7 +174,7 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..4107898 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -182,7 +182,7 @@ static void model_6fx_init(device_t cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -197,7 +197,7 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 9b92dcc..74d053e 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -18,7 +18,7 @@ static void model_6xx_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ca40515..e29b1e3 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -18,7 +18,7 @@ static void model_f0x_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index dbb5cd0..2cae97a 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -18,7 +18,7 @@ static void model_f1x_init(device_t dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 53eb75e..55d631b 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -23,10 +23,10 @@ static void model_f2x_init(device_t cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index f8d9ca6..f566c33 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -23,10 +23,10 @@ static void model_f3x_init(device_t cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 260b60a..b1a1e4f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -23,10 +23,10 @@ static void model_f4x_init(device_t cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..eb1de4b 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -32,7 +32,7 @@ static void c3_init(device_t dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..e09112c 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -205,7 +205,7 @@ static void c7_init(device_t dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
@@ -214,7 +214,7 @@ static struct device_operations cpu_dev_ops = { };
/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact - * ID, the cpu mask (stepping) is masked out and the check is repeated. This + * ID, the CPU mask (stepping) is masked out and the check is repeated. This * allows us to keep the table significantly smaller. */
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..7298386 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -183,7 +183,7 @@ static void nano_init(device_t dev) /* Set up Memory Type Range Registers */ x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index c82edfd..01c985a 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -53,7 +53,7 @@ _start: * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. - * If you cpu needs it you can write a cpu dependent version of + * If you CPU needs it you can write a CPU dependent version of * entry16.inc. */
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 09b6b9e..41793a8 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -239,10 +239,10 @@ static int lapic_start_cpu(unsigned long apicid) static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic + * Only starting one CPU at a time let's me remove the logic * for select the stack from assembly language. * - * In addition communicating by variables to the cpu I + * In addition communicating by variables to the CPU I * am starting allows me to verify it has started before * start_cpu returns. */ @@ -298,12 +298,12 @@ int start_cpu(device_t cpu) cpu->enabled = 0; cpu->initialized = 0;
- /* Start the cpu */ + /* Start the CPU */ result = lapic_start_cpu(apicid);
if (result) { result = 0; - /* Wait 1s or until the new cpu calls in */ + /* Wait 1s or until the new CPU calls in */ for(count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; @@ -507,23 +507,23 @@ void initialize_cpus(struct bus *cpu_bus) struct device_path cpu_path; struct cpu_info *info;
- /* Find the info struct for this cpu */ + /* Find the info struct for this CPU */ info = cpu_info();
#if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ enable_lapic();
- /* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_APIC; + /* Get the device path of the boot CPU */ + cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else - /* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_CPU; - cpu_path.cpu.id = 0; + /* Get the device path of the boot CPU */ + cpu_path.type = DEVICE_PATH_CPU; + cpu_path.cpu.id = 0; #endif
- /* Find the device structure for the boot cpu */ + /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index e83c23d..5ed21d0 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -331,7 +331,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) device_t new; int apic_id;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC;
/* Assuming linear APIC space allocation. */ @@ -341,10 +341,10 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) } cpu_path.apic.apic_id = apic_id;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); if (new == NULL) { - printk(BIOS_CRIT, "Could not allocte cpu device\n"); + printk(BIOS_CRIT, "Could not allocte CPU device\n"); max_cpus--; } cpus[i].dev = new; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index c08c391..fcb92f4 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -100,7 +100,7 @@ ap_start: mov idt_ptr, %ebx lidt (%ebx)
- /* Obtain cpu number. */ + /* Obtain CPU number. */ movl ap_count, %eax 1: movl %eax, %ecx @@ -114,7 +114,7 @@ ap_start: movl stack_top, %edx subl %eax, %edx mov %edx, %esp - /* Save cpu number. */ + /* Save CPU number. */ mov %ecx, %esi
/* Determine if one should check microcode versions. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 478ae8c..171836e 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -52,7 +52,7 @@ extern unsigned char _binary_smmstub_start[]; /* This is the SMM handler that the stub calls. It is encoded as an rmodule. */ extern unsigned char _binary_smm_start[];
-/* Per cpu minimum stack size. */ +/* Per CPU minimum stack size. */ #define SMM_MINIMUM_STACK_SIZE 32
/* @@ -79,7 +79,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, struct smm_entry_ins entry = { .jmp_rel = 0xe9 };
/* Each entry point has an IP value of 0x8000. The SMBASE for each - * cpu is different so the effective address of the entry instruction + * CPU is different so the effective address of the entry instruction * is different. Therefore, the relative displacement for each entry * instruction needs to be updated to reflect the current effective * IP. Additionally, the IP result from the jmp instruction is @@ -130,7 +130,7 @@ static void *smm_stub_place_stacks(char *base, int size, }
/* Place the staggered entry points for each CPU. The entry points are - * staggered by the per cpu SMM save state size extending down from + * staggered by the per CPU SMM save state size extending down from * SMM_ENTRY_OFFSET. */ static void smm_stub_place_staggered_entry_points(char *base, const struct smm_loader_params *params, const struct rmodule *smm_stub) @@ -264,7 +264,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) stub_params->runtime.smbase = (u32)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size;
- /* Initialize the APIC id to cpu number table to be 1:1 */ + /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) stub_params->runtime.apic_id_to_cpu[i] = i;
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 083cb57..73e2da4 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -45,15 +45,15 @@ smbase: .long 0 save_state_size: .long 0 -/* apic_to_cpu_num is a table mapping the default APIC id to cpu num. If the - * APIC id is found at the given index, the contiguous cpu number is index +/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the + * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ apic_to_cpu_num: .fill CONFIG_MAX_CPUS,1,0xff /* end struct smm_runtime */
.data -/* Provide fallback stack to use when a valid cpu number cannot be found. */ +/* Provide fallback stack to use when a valid CPU number cannot be found. */ fallback_stack_bottom: .skip 128 fallback_stack_top: @@ -119,7 +119,7 @@ smm_trampoline32: inc %ecx cmp $CONFIG_MAX_CPUS, %ecx jne 1b - /* This is bad. One cannot find a stack entry because a cpu num could + /* This is bad. One cannot find a stack entry because a CPU num could * not be assigned. Use the fallback stack and check this condition in * C handler. */ movl $(fallback_stack_top), %esp diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bdc9771..309c1cb 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -118,7 +118,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 CPU cores before * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. @@ -239,7 +239,7 @@ skip_smrr: outb %al, %dx movb $'-', %al outb %al, %dx - /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ + /* calculate ascii of CPU number. More than 9 cores? -> FIXME */ movb %cl, %al addb $'0', %al outb %al, %dx