Patch set updated for coreboot: 2b97386 fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
Martin Roth (martin.roth@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5791
-gerrit
commit 2b973863821ac3762d6a1e46a2aeb4ef24c34b43 Author: Martin Roth gaumless@gmail.com Date: Mon May 12 21:55:00 2014 -0600
fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
While similar to the Bay Trail-M/D code based on the MRC, there are many differences as well: - Obviously, uses the FSP instead of the MRC binaries. - FSP does additional hardware setup, so coreboot doesn't need to. - Different microcode & microcode loading method - Uses the cache_as_ram.inc from the FSP Driver - Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC: - Updated IRQ Routing - Different FADT implementation.
This was validated with FSP: BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5 MD5: 9360cd915f0d3e4116bbc782233d7b91
Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4 Signed-off-by: Martin Roth gaumless@gmail.com --- src/soc/intel/Kconfig | 1 + src/soc/intel/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/Kconfig | 162 +++++ src/soc/intel/fsp_baytrail/Makefile.inc | 96 +++ src/soc/intel/fsp_baytrail/acpi.c | 574 +++++++++++++++++ src/soc/intel/fsp_baytrail/acpi/cpu.asl | 77 +++ src/soc/intel/fsp_baytrail/acpi/device_nvs.asl | 87 +++ src/soc/intel/fsp_baytrail/acpi/globalnvs.asl | 103 +++ src/soc/intel/fsp_baytrail/acpi/gpio.asl | 110 ++++ src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 55 ++ src/soc/intel/fsp_baytrail/acpi/irqlinks.asl | 493 ++++++++++++++ src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 43 ++ src/soc/intel/fsp_baytrail/acpi/lpc.asl | 167 +++++ src/soc/intel/fsp_baytrail/acpi/lpe.asl | 119 ++++ src/soc/intel/fsp_baytrail/acpi/lpss.asl | 712 +++++++++++++++++++++ src/soc/intel/fsp_baytrail/acpi/platform.asl | 73 +++ src/soc/intel/fsp_baytrail/acpi/scc.asl | 187 ++++++ src/soc/intel/fsp_baytrail/acpi/sleepstates.asl | 26 + src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 284 ++++++++ src/soc/intel/fsp_baytrail/acpi/usb.asl | 54 ++ src/soc/intel/fsp_baytrail/acpi/xhci.asl | 36 ++ src/soc/intel/fsp_baytrail/baytrail/acpi.h | 34 + src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 74 +++ src/soc/intel/fsp_baytrail/baytrail/device_nvs.h | 67 ++ src/soc/intel/fsp_baytrail/baytrail/ehci.h | 44 ++ src/soc/intel/fsp_baytrail/baytrail/gfx.h | 48 ++ src/soc/intel/fsp_baytrail/baytrail/gpio.h | 387 +++++++++++ src/soc/intel/fsp_baytrail/baytrail/iomap.h | 90 +++ src/soc/intel/fsp_baytrail/baytrail/iosf.h | 195 ++++++ src/soc/intel/fsp_baytrail/baytrail/irq.h | 165 +++++ src/soc/intel/fsp_baytrail/baytrail/lpc.h | 112 ++++ src/soc/intel/fsp_baytrail/baytrail/msr.h | 41 ++ src/soc/intel/fsp_baytrail/baytrail/nvm.h | 34 + src/soc/intel/fsp_baytrail/baytrail/nvs.h | 73 +++ src/soc/intel/fsp_baytrail/baytrail/pattrs.h | 65 ++ src/soc/intel/fsp_baytrail/baytrail/pci_devs.h | 241 +++++++ src/soc/intel/fsp_baytrail/baytrail/pcie.h | 102 +++ src/soc/intel/fsp_baytrail/baytrail/pmc.h | 307 +++++++++ src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 35 + src/soc/intel/fsp_baytrail/baytrail/reset.h | 36 ++ src/soc/intel/fsp_baytrail/baytrail/romstage.h | 52 ++ src/soc/intel/fsp_baytrail/baytrail/smm.h | 48 ++ src/soc/intel/fsp_baytrail/baytrail/spi.h | 68 ++ src/soc/intel/fsp_baytrail/baytrail/xhci.h | 56 ++ src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 112 ++++ src/soc/intel/fsp_baytrail/chip.c | 116 ++++ src/soc/intel/fsp_baytrail/chip.h | 212 ++++++ src/soc/intel/fsp_baytrail/cpu.c | 278 ++++++++ src/soc/intel/fsp_baytrail/ehci.c | 180 ++++++ src/soc/intel/fsp_baytrail/fsp/Kconfig | 31 + src/soc/intel/fsp_baytrail/fsp/Makefile.inc | 22 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 325 ++++++++++ src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 49 ++ src/soc/intel/fsp_baytrail/gpio.c | 236 +++++++ src/soc/intel/fsp_baytrail/iosf.c | 111 ++++ src/soc/intel/fsp_baytrail/lpss.c | 166 +++++ src/soc/intel/fsp_baytrail/memmap.c | 28 + src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 25 + .../intel/fsp_baytrail/microcode/microcode_blob.c | 25 + src/soc/intel/fsp_baytrail/northcluster.c | 226 +++++++ src/soc/intel/fsp_baytrail/nvm.c | 88 +++ src/soc/intel/fsp_baytrail/placeholders.c | 15 + src/soc/intel/fsp_baytrail/pmutil.c | 364 +++++++++++ src/soc/intel/fsp_baytrail/raminit.c | 45 ++ src/soc/intel/fsp_baytrail/ramstage.c | 138 ++++ src/soc/intel/fsp_baytrail/reset.c | 47 ++ src/soc/intel/fsp_baytrail/romstage/Makefile.inc | 26 + src/soc/intel/fsp_baytrail/romstage/pmc.c | 41 ++ .../intel/fsp_baytrail/romstage/report_platform.c | 88 +++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 239 +++++++ src/soc/intel/fsp_baytrail/romstage/uart.c | 38 ++ src/soc/intel/fsp_baytrail/sata.c | 94 +++ src/soc/intel/fsp_baytrail/sd.c | 68 ++ src/soc/intel/fsp_baytrail/smihandler.c | 406 ++++++++++++ src/soc/intel/fsp_baytrail/smm.c | 132 ++++ src/soc/intel/fsp_baytrail/southcluster.c | 658 +++++++++++++++++++ src/soc/intel/fsp_baytrail/spi.c | 652 +++++++++++++++++++ src/soc/intel/fsp_baytrail/tsc_freq.c | 84 +++ src/soc/intel/fsp_baytrail/usb.c | 44 ++ src/soc/intel/fsp_baytrail/xhci.c | 250 ++++++++ 80 files changed, 11493 insertions(+)
diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 07099b3..3ddbf28 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -1 +1,2 @@ source src/soc/intel/baytrail/Kconfig +source src/soc/intel/fsp_baytrail/Kconfig diff --git a/src/soc/intel/Makefile.inc b/src/soc/intel/Makefile.inc index ad79817..b2f3cde 100644 --- a/src/soc/intel/Makefile.inc +++ b/src/soc/intel/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_INTEL_BAYTRAIL) += baytrail +subdirs-$(CONFIG_SOC_INTEL_FSP_BAYTRAIL) += fsp_baytrail diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig new file mode 100644 index 0000000..220edf7 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -0,0 +1,162 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_INTEL_FSP_BAYTRAIL + bool + help + Bay Trail I part support using the Intel FSP. + +if SOC_INTEL_FSP_BAYTRAIL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select DYNAMIC_CBMEM + select HAVE_HARD_RESET + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select RELOCATABLE_MODULES + select PARALLEL_MP + select REG_SCRIPT + select SMP + select SPI_FLASH + select SSE2 + select TSC_CONSTANT_RATE + select TSC_SYNC_MFENCE + select UDELAY_TSC + select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD + select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD + select ROMSTAGE_RTC_INIT + +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/fsp_baytrail/bootblock/bootblock.c" + +config MMCONF_BASE_ADDRESS + hex + default 0x80000000 + help + This is set by the FSP + +config MAX_CPUS + int + default 4 + +config CPU_ADDR_BITS + int + default 36 + +config SMM_TSEG_SIZE + hex + default 0x100000 + help + This is set by the FSP + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config VGA_BIOS_ID + string + default "8086,0f31" + help + This is the default PCI ID for the Bay Trail graphics + devices. This string names the vbios rom in cbfs. + +config INCLUDE_MICROCODE_IN_BUILD + bool "Build in microcode patch" + default n + help + Enable if the microcode patch is available. For the + BayTrail - I processors, the filename should start with + "M01". Using a microcode patch for the incorrect BayTrail + SKU will lead to unpredictable results. + +config MICROCODE_INCLUDE_PATH + string "Microcode Include path" + default "../intel/cpu/baytrail/microcode" + depends on SUPPORT_CPU_UCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff10040 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0xcc00 + help + This should be updated when the microcode patch changes. + +config CBFS_SIZE + hex + default 0x200000 + help + On Bay Trail systems the firmware image has to store a lot more + than just coreboot, including: + - a firmware descriptor + - Intel Trusted Execution Engine firmware + This option specifies the maximum size of the CBFS portion in the + firmware image. + +config INCLUDE_ME + bool "Include the TXE" + default n + help + Build the TXE and descriptor.bin into the ROM image. If you want to use a + descriptor.bin and TXE file from the previous ROM image, you may not want + to build it in here. + +config ME_PATH + string + depends on INCLUDE_ME + help + The path of the TXE and Descriptor files. + +config LOCK_MANAGEMENT_ENGINE + bool "Lock TXE section" + default n + depends on INCLUDE_ME + help + The Intel Trusted Execution Engine supports preventing write accesses + from the host to the Management Engine section in the firmware + descriptor. If the ME section is locked, it can only be overwritten + with an external SPI flash programmer. You will want this if you + want to increase security of your ROM image once you are sure + that the ME firmware is no longer going to change. + + If unsure, say N. + +config ENABLE_BUILTIN_COM1 + bool "Enable built-in legacy Serial Port" + help + The Baytrail SOC has one legacy serial port. Choose this option to + configure the pads and enable it. This serial port can be used for + the debug console. + +config VGA_BIOS_FILE + string + default "../intel/cpu/baytrail/vbios/Baytrail_I_36_2_2/Vga.dat" if VGA_BIOS + +## Baytrail Specific FSP Kconfig +source src/soc/intel/fsp_baytrail/fsp/Kconfig + +endif #SOC_INTEL_FSP_BAYTRAIL diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc new file mode 100644 index 0000000..9ec6566 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -0,0 +1,96 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Google Inc. +# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +subdirs-y += microcode +subdirs-y += romstage +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../lib/fsp +subdirs-y += fsp + +ramstage-y += memmap.c +romstage-y += memmap.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c +ramstage-y += spi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c +ramstage-y += chip.c +ramstage-y += iosf.c +romstage-y += iosf.c +ramstage-y += northcluster.c +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-y += pmutil.c +romstage-y += raminit.c +ramstage-y += raminit.c +ramstage-y += ehci.c +ramstage-y += xhci.c +ramstage-y += southcluster.c +romstage-y += reset.c +ramstage-y += reset.c +ramstage-y += cpu.c +ramstage-y += sata.c +ramstage-y += acpi.c +ramstage-y += lpss.c +ramstage-y += sd.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c + +# Remove as ramstage gets fleshed out +ramstage-y += placeholders.c + +CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ +CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp + +# Run an intermediate step when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS +ifeq ($(CONFIG_INCLUDE_ME),y) +ifneq ($(CONFIG_ME_PATH),) +INTERMEDIATE:=baytrail_add_txe + +baytrail_add_txe: $(obj)/coreboot.pre $(IFDTOOL) + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 + printf " IFDTOOL txe.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/txe.bin \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + +endif +endif + diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c new file mode 100644 index 0000000..dece178 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -0,0 +1,574 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <baytrail/baytrail.h> +#include <device/pci_ids.h> +#include <baytrail/pci_devs.h> +#include <baytrail/acpi.h> +#include <string.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/irq.h> +#include <baytrail/iosf.h> +#include <arch/io.h> +#include <baytrail/msr.h> +#include <baytrail/pattrs.h> +#include <baytrail/pmc.h> +#include <cbmem.h> + +#include "chip.h" + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +/* C-state map without S0ix */ +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + /* C6NS with no L2 shrink */ + /* NOTE: this substate is above CPUID limit */ + .ctype = 2, /* ACPI C2 */ + .latency = 500, + .power = 10, + .resource = MWAIT_RES(5, 1), + }, + { + /* C6FS with full L2 shrink */ + .ctype = 3, /* ACPI C3 */ + .latency = 1500, /* 1.5ms worst case */ + .power = 10, + .resource = MWAIT_RES(5, 2), + } +}; + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + /* Top of Low Memory (start of resource allocation) */ + gnvs->tolm = nc_read_top_of_low_memory(); + +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif +} + +static int acpi_sci_irq(void) +{ + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + int scis; + static int sci_irq; + + if (sci_irq) + return sci_irq; + + /* Determine how SCI is routed. */ + scis = read32(actl) & SCIS_MASK; + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +/** + * Fill in the fadt with generic values that can be overridden later. + */ + +typedef struct soc_intel_fsp_baytrail_config config_t; + +void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + struct device *lpcdev = dev_find_slot(FADT_SOC_LPC_DEV); + u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; + config_t *config = lpcdev->chip_info; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + /* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ + + /* FADT Header Structure */ + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + /* ACPI Pointers */ + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ + + /* System Management */ + fadt->sci_int = acpi_sci_irq(); +#if IS_ENABLED(CONFIG_BAYTRAIL_SMM) + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; +#else + fadt->smi_cmd = 0x00; /* disable SMM */ + fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */ + + /* Enable ACPI */ + outl(inl(pmbase + 4) | 0x01, pmbase + 4); +#endif + + /* Power Control */ + fadt->s4bios_req = 0x00; + fadt->pstate_cnt = 0x00; + + /* Control Registers - Base Address */ + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x00; /* Not Used */ + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x00; /* Not Used */ + fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe1_blk = 0x00; /* Not Used */ + + /* Control Registers - Length */ + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ + fadt->pm2_cnt_len = 1; /* 8 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0D; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */ + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xCF9; + fadt->reset_reg.addrh = 0x00; + fadt->reset_value = 6; + + /* Reserved Bits */ + fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + + /* Extended ACPI Pointers */ + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0x00; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0x00; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x00; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x00; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x00; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x00; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x00; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x00; + + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} +static acpi_tstate_t baytrail_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +static int generate_T_state_entries(int core, int cores_per_package) +{ + int len; + + /* Indicate SW_ALL coordination for T-states */ + len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + len += acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + len += acpigen_write_TPC("\TLVL"); + + /* Write TSS table for MSR access */ + len += acpigen_write_TSS_package( + ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); + + return len; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static int generate_P_state_entries(int core, int cores_per_package) +{ + int len, len_pss; + int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + int vid, vid_turbo, vid_min, vid_max, vid_range_2; + u32 control_status; + const struct pattrs *pattrs = pattrs_get(); + msr_t msr; + + /* Inputs from CPU attributes */ + ratio_max = pattrs->iacore_ratios[IACORE_MAX]; + ratio_min = pattrs->iacore_ratios[IACORE_LFM]; + vid_max = pattrs->iacore_vids[IACORE_MAX]; + vid_min = pattrs->iacore_vids[IACORE_LFM]; + + /* Hardware coordination of P-states */ + coord_type = HW_ALL; + + /* Max Non-Turbo Frequency */ + clock_max = (ratio_max * pattrs->bclk_khz) / 1000; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + msr = rdmsr(MSR_PKG_POWER_LIMIT); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + len = acpigen_write_empty_PCT(); + + /* Write _PPC with NVS specified limit on supported P-state */ + len += acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + len += acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + len += acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = 1; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > 15) { /* ACPI max is 15 ratios */ + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + len_pss = acpigen_write_package(num_entries + 2); + + ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; + vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; + control_status = (ratio_turbo << 8) | vid_turbo; + + /* Add entry for Turbo ratio */ + len_pss += acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } else { + /* _PSS package count without Turbo */ + len_pss = acpigen_write_package(num_entries + 1); + ratio_turbo = ratio_max; + vid_turbo = vid_max; + } + + /* First regular entry is max non-turbo ratio */ + control_status = (ratio_max << 8) | vid_max; + len_pss += acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control */ + control_status); /*status*/ + + /* Set up ratio and vid ranges for VID calculation */ + ratio_range_2 = (ratio_turbo - ratio_min) * 2; + vid_range_2 = (vid_turbo - vid_min) * 2; + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate VID for this ratio */ + vid = ((ratio - ratio_min) * vid_range_2) / + ratio_range_2 + vid_min; + /* Round up if remainder */ + if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) + vid++; + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * pattrs->bclk_khz) / 1000; + control_status = (ratio << 8) | (vid & 0xff); + + len_pss += acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } + + /* Fix package length */ + len_pss--; + acpigen_patch_len(len_pss); + + return len + len_pss; +} + +void generate_cpu_entries(void) +{ + int len_pr, core; + int pcontrol_blk = get_pmbase(), plen = 6; + const struct pattrs *pattrs = pattrs_get(); + + for (core=0; core<pattrs->num_cpus; core++) { + if (core > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor _PR.CPUx */ + len_pr = acpigen_write_processor( + core, pcontrol_blk, plen); + + /* Generate P-state tables */ + len_pr += generate_P_state_entries( + core, pattrs->num_cpus); + + /* Generate C-state tables */ + len_pr += acpigen_write_CST_package( + cstate_map, ARRAY_SIZE(cstate_map)); + + /* Generate T-state tables */ + len_pr += generate_T_state_entries( + core, pattrs->num_cpus); + + len_pr--; + acpigen_patch_len(len_pr); + } +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci_irq = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci_irq >= 20) + sci_flags |= MP_IRQ_POLARITY_LOW; + else + sci_flags |= MP_IRQ_POLARITY_HIGH; + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, + sci_flags); + + return current; +} diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl new file mode 100644 index 0000000..16f62ba --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These devices are created at runtime */ +External (_PR.CPU0, DeviceObj) +External (_PR.CPU1, DeviceObj) +External (_PR.CPU2, DeviceObj) +External (_PR.CPU3, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CPU0, 0x81) // _CST + Notify (_PR.CPU1, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CPU2, 0x81) // _CST + Notify (_PR.CPU3, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CPU0, 0x80) // _PPC + Notify (_PR.CPU1, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CPU2, 0x80) // _PPC + Notify (_PR.CPU3, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CPU0, 0x82) // _TPC + Notify (_PR.CPU1, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CPU2, 0x82) // _TPC + Notify (_PR.CPU3, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 4)) { + Return (Package() {_PR.CPU0, _PR.CPU1, _PR.CPU2, _PR.CPU3}) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package() {_PR.CPU0, _PR.CPU1}) + } Else { + Return (Package() {_PR.CPU0}) + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl b/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl new file mode 100644 index 0000000..fce7b53 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Device Enabled in ACPI Mode */ + +S0EN, 8, // SDMA Enable +S1EN, 8, // I2C1 Enable +S2EN, 8, // I2C2 Enable +S3EN, 8, // I2C3 Enable +S4EN, 8, // I2C4 Enable +S5EN, 8, // I2C5 Enable +S6EN, 8, // I2C6 Enable +S7EN, 8, // I2C7 Enable +S8EN, 8, // SDMA2 Enable +S9EN, 8, // SPI Enable +SAEN, 8, // PWM1 Enable +SBEN, 8, // PWM2 Enable +SCEN, 8, // UART2 Enable +SDEN, 8, // UART2 Enable +C0EN, 8, // MMC Enable +C1EN, 8, // SDIO Enable +C2EN, 8, // SD Card Enable +LPEN, 8, // LPE Enable + +/* BAR 0 */ + +S0B0, 32, // SDMA BAR0 +S1B0, 32, // I2C1 BAR0 +S2B0, 32, // I2C2 BAR0 +S3B0, 32, // I2C3 BAR0 +S4B0, 32, // I2C4 BAR0 +S5B0, 32, // I2C5 BAR0 +S6B0, 32, // I2C6 BAR0 +S7B0, 32, // I2C7 BAR0 +S8B0, 32, // SDMA2 BAR0 +S9B0, 32, // SPI BAR0 +SAB0, 32, // PWM1 BAR0 +SBB0, 32, // PWM2 BAR0 +SCB0, 32, // UART1 BAR0 +SDB0, 32, // UART2 BAR0 +C0B0, 32, // MMC BAR0 +C1B0, 32, // SDIO BAR0 +C2B0, 32, // SD Card BAR0 +LPB0, 32, // LPE BAR0 + +/* BAR 1 */ + +S0B1, 32, // SDMA BAR1 +S1B1, 32, // I2C1 BAR1 +S2B1, 32, // I2C2 BAR1 +S3B1, 32, // I2C3 BAR1 +S4B1, 32, // I2C4 BAR1 +S5B1, 32, // I2C5 BAR1 +S6B1, 32, // I2C6 BAR1 +S7B1, 32, // I2C7 BAR1 +S8B1, 32, // SDMA2 BAR1 +S9B1, 32, // SPI BAR1 +SAB1, 32, // PWM1 BAR1 +SBB1, 32, // PWM2 BAR1 +SCB1, 32, // UART1 BAR1 +SDB1, 32, // UART2 BAR1 +C0B1, 32, // MMC BAR1 +C1B1, 32, // SDIO BAR1 +C2B1, 32, // SD Card BAR1 +LPB1, 32, // LPE BAR1 + +/* Extra */ + +LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl new file mode 100644 index 0000000..696390d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + PCNT, 8, // 0x11 - Processor count + TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS + + /* Device Config */ + Offset (0x20), + S5U0, 8, // 0x20 - Enable USB0 in S5 + S5U1, 8, // 0x21 - Enable USB1 in S5 + S3U0, 8, // 0x22 - Enable USB0 in S3 + S3U1, 8, // 0x23 - Enable USB1 in S3 + TACT, 8, // 0x24 - Thermal Active trip point + TPSV, 8, // 0x25 - Thermal Passive trip point + TCRT, 8, // 0x26 - Thermal Critical trip point + DPTE, 8, // 0x27 - Enable DPTF + + /* Base addresses */ + Offset (0x30), + CMEM, 32, // 0x30 - CBMEM TOC + TOLM, 32, // 0x34 - Top of Low Memory + CBMC, 32, // 0x38 - coreboot mem console pointer + + Offset (0x1000), + #include <soc/intel/fsp_baytrail/acpi/device_nvs.asl> +} + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) + Store (One, \S3U1) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) + Store (Zero, \S3U1) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) + Store (One, \S5U1) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) + Store (Zero, \S5U1) +} diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl new file mode 100644 index 0000000..f2618a8 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/gpio.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <soc/intel/fsp_baytrail/baytrail/iomap.h> +#include <soc/intel/fsp_baytrail/baytrail/irq.h> + +/* SouthCluster GPIO */ +Device (GPSC) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* NorthCluster GPIO */ +Device (GPNC) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_NC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* SUS GPIO */ +Device (GPSS) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SUS_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h new file mode 100644 index 0000000..e3a23d8 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronics Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h + * to generate the ACPI IRQ routing for the mainboard being compiled. + * This method uses #defines in irqroute.h along with the macros contained + * in this file to generate an IRQ routing for each PCI device in the system. + */ +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, _SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +/* Include the mainboard irq route definition */ +#include "irqroute.h" diff --git a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl b/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl new file mode 100644 index 0000000..5fcee45 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LNKA) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTA) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTA + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTA, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTB) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTB + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTB, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTC) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTC + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTC, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 4) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTD) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTD + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTD, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 5) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTE) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTE + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTE, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 6) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTF) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTF + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTF, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 7) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTG) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTG + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTG, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 8) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTH) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTH + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTH, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl new file mode 100644 index 0000000..940f853 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// PCI Interrupt Routing +Method(_PRT) +{ + /* + * PICM comes from _PIC, which returns the following: + * 0 – PIC mode + * 1 – APIC mode + * 2 – SAPIC mode + */ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl new file mode 100644 index 0000000..408d2b4 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + // Include mainboard's superio.asl file. + #include "acpi/superio.asl" + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif +} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpe.asl b/src/soc/intel/fsp_baytrail/acpi/lpe.asl new file mode 100644 index 0000000..71a2746 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/lpe.asl @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LPEA) +{ + Name (_HID, "80860F28") + Name (_CID, "80860F28") + Name (_UID, 1) + Name (_DDN, "Low Power Audio Controller") + Name (_PR0, Package () { PLPE }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) + Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) + Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP2_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_IPC2HOST_IRQ + } + }) + + Method (_CRS) + { + /* Update BAR0 from NVS */ + CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) + Store (\LPB0, BAS0) + + /* Update BAR1 from NVS */ + CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) + Store (\LPB1, BAS1) + + /* Update LPE FW from NVS */ + CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) + Store (\LPFW, BAS2) + + /* Append any Mainboard defined GPIOs */ + If (CondRefOf (^GBUF, Local0)) { + ConcatenateResTemplate (^RBUF, Local0, Local1) + Return (Local1) + } + + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\LPEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, LPB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + PowerResource (PLPE, 0, 0) + { + Method (_STA) + { + Return (1) + } + + Method (_OFF) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_ON) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpss.asl b/src/soc/intel/fsp_baytrail/acpi/lpss.asl new file mode 100644 index 0000000..0f8f746 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/lpss.asl @@ -0,0 +1,712 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (SDM1) +{ + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_DDN, "DMA Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA1_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (SDM2) +{ + Name (_HID, "INTL9C60") + Name (_UID, 2) + Name (_DDN, "DMA Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA2_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S8B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S8EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (I2C1) +{ + Name (_HID, "80860F41") + Name (_UID, 1) + Name (_DDN, "I2C Controller #1") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C1_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C2) +{ + Name (_HID, "80860F41") + Name (_UID, 2) + Name (_DDN, "I2C Controller #2") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C2_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C3) +{ + Name (_HID, "80860F41") + Name (_UID, 3) + Name (_DDN, "I2C Controller #3") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C3_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S3B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S3EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S3B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C4) +{ + Name (_HID, "80860F41") + Name (_UID, 4) + Name (_DDN, "I2C Controller #4") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C4_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S4B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S4EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S4B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C5) +{ + Name (_HID, "80860F41") + Name (_UID, 5) + Name (_DDN, "I2C Controller #5") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C5_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S5B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S5B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C6) +{ + Name (_HID, "80860F41") + Name (_UID, 6) + Name (_DDN, "I2C Controller #6") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C6_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S6B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S6B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C7) +{ + Name (_HID, "80860F41") + Name (_UID, 7) + Name (_DDN, "I2C Controller #7") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C7_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S7B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S7EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S7B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SPI1) +{ + Name (_HID, "80860F0E") + Name (_UID, 1) + Name (_DDN, "SPI Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_SPI_IRQ + } + FixedDMA (0x0, 0x0, Width32Bit, ) + FixedDMA (0x1, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S9B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S9EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S9B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (PWM1) +{ + Name (_HID, "80860F09") + Name (_UID, 1) + Name (_DDN, "PWM Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SAB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SAEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (PWM2) +{ + Name (_HID, "80860F09") + Name (_UID, 2) + Name (_DDN, "PWM Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SBB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SBEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (UAR1) +{ + Name (_HID, "80860F0A") + Name (_UID, 1) + Name (_DDN, "HS-UART Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART1_IRQ + } + FixedDMA (0x2, 0x2, Width32Bit, ) + FixedDMA (0x3, 0x3, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SCB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SCEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SCB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (UAR2) +{ + Name (_HID, "80860F0A") + Name (_UID, 2) + Name (_DDN, "HS-UART Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART2_IRQ + } + FixedDMA (0x4, 0x4, Width32Bit, ) + FixedDMA (0x5, 0x5, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SDB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SDEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SDB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/platform.asl b/src/soc/intel/fsp_baytrail/acpi/platform.asl new file mode 100644 index 0000000..e069392 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/soc/intel/fsp_baytrail/acpi/scc.asl b/src/soc/intel/fsp_baytrail/acpi/scc.asl new file mode 100644 index 0000000..7181fb1 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/scc.asl @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (EMMC) +{ + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_DDN, "eMMC Controller 4.5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_EMMC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C0B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Device (EM45) + { + /* Slot 0, Function 8 */ + Name (_ADR, 0x8) + + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDIO) +{ + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_UID, 2) + Name (_DDN, "SDIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SDIO_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SDCD) +{ + Name (_HID, "80860F16") + Name (_CID, "PNP0D40") + Name (_UID, 3) + Name (_DDN, "SD Card Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SD_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl new file mode 100644 index 0000000..b21656c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(_S0, Package(){0x0,0x0,0x0,0x0}) +// Name(_S1, Package(){0x1,0x1,0x0,0x0}) +Name(_S4, Package(){0x6,0x6,0x0,0x0}) +Name(_S5, Package(){0x7,0x7,0x0,0x0}) + diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl new file mode 100644 index 0000000..7136e14 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <soc/intel/fsp_baytrail/baytrail/iomap.h> +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include "../baytrail/baytrail.h" + +Scope() +{ + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + // Intel Legacy Block + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field (ILBS, AnyAcc, NoLock, Preserve) + { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfeafffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, + 0x00100000,,, PMEM) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) + }) + + // Update PCI resource area + CreateDwordField(MCRS, PMEM._MIN, PMIN) + CreateDwordField(MCRS, PMEM._MAX, PMAX) + CreateDwordField(MCRS, PMEM._LEN, PLEN) + + // TOLM is BMBOUND accessible from IOSF so is saved in NVS + Store (\TOLM, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +/* IOSF MBI Interface for kernel access */ +Device (IOSF) +{ + Name (_HID, "INT33BD") + Name (_CID, "INT33BD") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + /* MCR / MDR / MCRX */ + Memory32Fixed (ReadWrite, 0, 12, RBAR) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) + Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + Return (^RBUF) + } +} + +// LPC Bridge 0:1f.0 +#include "lpc.asl" + +#if INCLUDE_EHCI +// USB EHCI 0:1d.0 +#include "usb.asl" +#endif + +#if INCLUDE_XHCI +// USB XHCI 0:14.0 +#include "xhci.asl" +#endif + +// IRQ routing for each PCI device +#include "irqroute.asl" + +Scope (_SB) +{ + // GPIO Devices + #include "gpio.asl" + +#if INCLUDE_LPSS + // LPSS Devices + #include "lpss.asl" +#endif + +#if INCLUDE_SCC + // SCC Devices + #include "scc.asl" +#endif + +#if INCLUDE_LPE + // LPE Device + #include "lpe.asl" +#endif +} diff --git a/src/soc/intel/fsp_baytrail/acpi/usb.asl b/src/soc/intel/fsp_baytrail/acpi/usb.asl new file mode 100644 index 0000000..ebc32ae --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/usb.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel Baytrail USB support */ + +// EHCI Controller 0:1d.0 + +Device (EHC1) +{ + Name(_ADR, 0x001d0000) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + } +} + diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl new file mode 100644 index 0000000..4d5367a --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/xhci.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + Name (_PRW, Package () { 0x0d, 3 }) + Name (_S3D, 3) /* Highest D state in S3 state */ + + Device (RHUB) + { + Name (_ADR, 0x00000000) + Device (PRT1) { Name (_ADR, 1) } + Device (PRT2) { Name (_ADR, 2) } + Device (PRT3) { Name (_ADR, 3) } + Device (PRT4) { Name (_ADR, 4) } + } +} diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h new file mode 100644 index 0000000..d796873 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_ACPI_H_ +#define _BAYTRAIL_ACPI_H_ + +#include <arch/acpi.h> +#include <baytrail/nvs.h> + +void acpi_create_intel_hpet(acpi_hpet_t * hpet); +void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); +unsigned long acpi_madt_irq_overrides(unsigned long current); +void acpi_init_gnvs(global_nvs_t *gnvs); + +#endif /* _BAYTRAIL_ACPI_H_ */ + diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h new file mode 100644 index 0000000..d3a2377 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ +#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ + +#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS +#define CPU_MICROCODE_CBFS_LEN 0x26000 + +/* Southbridge internal device IO BARs (Set to match FSP settings) */ +#define SMBUS_IO_BASE 0xefa0 +#define SMBUS_SLAVE_ADDR 0x24 +#define DEFAULT_GPIOBASE 0x0500 +#define DEFAULT_ABASE 0x0400 + +/* Southbridge internal device MEM BARs (Set to match FSP settings) */ +#define DEFAULT_IBASE 0xfed08000 +#define DEFAULT_PBASE 0xfed03000 +#define DEFAULT_RCBA 0xfed1c000 + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +/* SOC types */ +#define SOC_TYPE_BAYTRAIL 0x0F1C + +#ifndef __ASSEMBLER__ +static inline void barrier(void) { asm("" ::: "memory"); } + +#define SKPAD 0xFC + +int bridge_silicon_revision(void); +void rangeley_early_initialization(void); + +#ifndef __PRE_RAM__ +/* soc.c */ +int soc_silicon_revision(void); +int soc_silicon_type(void); +int soc_silicon_supported(int type, int rev); +void soc_enable(device_t dev); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); +void report_platform_info(void); + +#endif /* __PRE_RAM__ */ +#endif /* __ASSEMBLER__ */ + +#endif /* __ACPI__ */ +#endif diff --git a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h new file mode 100644 index 0000000..a06ca70 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_DEVICE_NVS_H_ +#define _BAYTRAIL_DEVICE_NVS_H_ + +#include <stdint.h> + +/* Offset in Global NVS where this structure lives */ +#define DEVICE_NVS_OFFSET 0x1000 + +#define LPSS_NVS_SIO_DMA1 0 +#define LPSS_NVS_I2C1 1 +#define LPSS_NVS_I2C2 2 +#define LPSS_NVS_I2C3 3 +#define LPSS_NVS_I2C4 4 +#define LPSS_NVS_I2C5 5 +#define LPSS_NVS_I2C6 6 +#define LPSS_NVS_I2C7 7 +#define LPSS_NVS_SIO_DMA2 8 +#define LPSS_NVS_SPI 9 +#define LPSS_NVS_PWM1 10 +#define LPSS_NVS_PWM2 11 +#define LPSS_NVS_HSUART1 12 +#define LPSS_NVS_HSUART2 13 + +#define SCC_NVS_MMC 0 +#define SCC_NVS_SDIO 1 +#define SCC_NVS_SD 2 + +typedef struct { + /* Device Enabled in ACPI Mode */ + u8 lpss_en[14]; + u8 scc_en[3]; + u8 lpe_en; + + /* BAR 0 */ + u32 lpss_bar0[14]; + u32 scc_bar0[3]; + u32 lpe_bar0; + + /* BAR 1 */ + u32 lpss_bar1[14]; + u32 scc_bar1[3]; + u32 lpe_bar1; + + /* Extra */ + u32 lpe_fw; /* LPE Firmware */ +} __attribute__((packed)) device_nvs_t; + +#endif diff --git a/src/soc/intel/fsp_baytrail/baytrail/ehci.h b/src/soc/intel/fsp_baytrail/baytrail/ehci.h new file mode 100644 index 0000000..a1edd6d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/ehci.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_EHCI_H +#define BAYTRAIL_EHCI_H + +/* EHCI PCI Registers */ +#define EHCI_CMD_STS 0x04 +# define INTRDIS (1 << 10) +#define EHCI_SBRN_FLA_PWC 0x60 +# define PORTWKIMP (1 << 16) +# define PORTWKCAPMASK (0x3ff << 17) +#define EHCI_USB2PDO 0x64 + +/* EHCI Memory Registers */ +#define USB2CMD 0x20 +# define USB2CMD_ASE (1 << 5) +# define USB2CMD_PSE (1 << 4) +# define USB2CMD_HCRESET (1 << 1) +# define USB2CMD_RS (1 << 0) +#define USB2STS 0x24 +# define USB2STS_HCHALT (1 << 12) + +/* RCBA EHCI Registers */ +#define RCBA_FUNC_DIS 0x220 +# define RCBA_EHCI_DIS (1 << 0) + +#endif /* BAYTRAIL_EHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/gfx.h b/src/soc/intel/fsp_baytrail/baytrail/gfx.h new file mode 100644 index 0000000..655615d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/gfx.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_GFX_H_ +#define _BAYTRAIL_GFX_H_ + +/* + * PCI config registers. + */ + +#define GGC 0x50 +# define GGC_VGA_DISABLE (1 << 1) +# define GGC_GTT_SIZE_MASK (3 << 8) +# define GGC_GTT_SIZE_0MB (0 << 8) +# define GGC_GTT_SIZE_1MB (1 << 8) +# define GGC_GTT_SIZE_2MB (2 << 8) +# define GGC_GSM_SIZE_MASK (0x1f << 3) +# define GGC_GSM_SIZE_0MB (0 << 3) +# define GGC_GSM_SIZE_32MB (1 << 3) +# define GGC_GSM_SIZE_64MB (2 << 3) +# define GGC_GSM_SIZE_128MB (4 << 3) + +#define GSM_BASE 0x5c +#define GTT_BASE 0x70 + +#define MSAC 0x62 +#define APERTURE_SIZE_MASK (3 << 1) +#define APERTURE_SIZE_128MB (0 << 1) +#define APERTURE_SIZE_256MB (1 << 1) +#define APERTURE_SIZE_512MB (3 << 1) + +#endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h new file mode 100644 index 0000000..4c9e8a8 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -0,0 +1,387 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_GPIO_H_ +#define _BAYTRAIL_GPIO_H_ + +#include <stdint.h> +#include <arch/io.h> +#include <baytrail/iomap.h> + +/* #define GPIO_DEBUG */ + +/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) +#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) +#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) + +/* DIRQ registers start at pad base + 0x980 */ +#define PAD_BASE_DIRQ_OFFSET 0x980 + +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 + +/* Legacy IO register base */ +#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) +#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF + +#define LEGACY_USE_SEL_REG 0x00 +#define LEGACY_IO_SEL_REG 0x04 +#define LEGACY_GP_LVL_REG 0x08 +#define LEGACY_TPE_REG 0x0C +#define LEGACY_TNE_REG 0x10 +#define LEGACY_TS_REG 0x14 +#define LEGACY_WAKE_EN_REG 0x18 + +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +/* GPIO legacy IO register settings */ +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_PEDGE_DISABLE 0 +#define GPIO_PEDGE_ENABLE 1 + +#define GPIO_NEDGE_DISABLE 0 +#define GPIO_NEDGE_ENABLE 1 + +/* config0[29] - Disable second mask */ +#define PAD_MASK2_DISABLE (1 << 29) + +/* config0[27] - Direct Irq En */ +#define PAD_IRQ_EN (1 << 27) + +/* config0[26] - gd_tne */ +#define PAD_TNE_IRQ (1 << 26) + +/* config0[25] - gd_tpe */ +#define PAD_TPE_IRQ (1 << 25) + +/* config0[24] - Gd Level */ +#define PAD_LEVEL_IRQ (1 << 24) +#define PAD_EDGE_IRQ (0 << 24) + +/* config0[17] - Slow clkgate / glitch filter */ +#define PAD_SLOWGF_ENABLE (1 << 17) + +/* config0[16] - Fast clkgate / glitch filter */ +#define PAD_FASTGF_ENABLE (1 << 16) + +/* config0[15] - Hysteresis enable (inverted) */ +#define PAD_HYST_DISABLE (1 << 15) +#define PAD_HYST_ENABLE (0 << 15) + +/* config0[14:13] - Hysteresis control */ +#define PAD_HYST_CTRL_DEFAULT (2 << 13) + +/* config0[11] - Bypass Flop */ +#define PAD_FLOP_BYPASS (1 << 11) +#define PAD_FLOP_ENABLE (0 << 11) + +/* config0[10:9] - Pull str */ +#define PAD_PU_2K (0 << 9) +#define PAD_PU_10K (1 << 9) +#define PAD_PU_20K (2 << 9) +#define PAD_PU_40K (3 << 9) + +/* config0[8:7] - Pull assign */ +#define PAD_PULL_DISABLE (0 << 7) +#define PAD_PULL_UP (1 << 7) +#define PAD_PULL_DOWN (2 << 7) + +/* config0[2:0] - Func. pin mux */ +#define PAD_FUNC0 0x0 +#define PAD_FUNC1 0x1 +#define PAD_FUNC2 0x2 +#define PAD_FUNC3 0x3 +#define PAD_FUNC4 0x4 +#define PAD_FUNC5 0x5 +#define PAD_FUNC6 0x6 + +/* pad config0 power-on values - We will not often want to change these */ +#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ + PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ + PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) + +/* pad config1 reg power-on values - Shouldn't need to change this */ +#define PAD_CONFIG1_DEFAULT 0x8000 + +/* pad_val[2] - Iinenb - active low */ +#define PAD_VAL_INPUT_DISABLE (1 << 2) +#define PAD_VAL_INPUT_ENABLE (0 << 2) + +/* pad_val[1] - Ioutenb - active low */ +#define PAD_VAL_OUTPUT_DISABLE (1 << 1) +#define PAD_VAL_OUTPUT_ENABLE (0 << 1) + +/* Input / Output state should usually be mutually exclusive */ +#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) + +/* pad_val[0] - Value */ +#define PAD_VAL_HIGH (1 << 0) +#define PAD_VAL_LOW (0 << 0) + +/* pad_val reg power-on default varies by pad, and apparently can cause issues + * if not set correctly, even if the pin isn't configured as GPIO. */ +#define PAD_VAL_DEFAULT PAD_VAL_INPUT + +/* Configure GPIOs as MMIO by default */ +#define GPIO_INPUT_PU_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_LEGACY_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .is_gpio = 1 } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + + +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } + +/* Define no-pull / PU / PD configs for each functional config option */ +#define GPIO_FUNC(_func, _pudir, _str) \ + { .use_sel = GPIO_USE_MMIO, \ + .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ + PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } + +/* Default functional configs -- no PU */ +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) + +/* ACPI GPIO routing. Assume everything is externally pulled and negative edge + * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ +#define GPIO_ACPI_SCI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .sci = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_WAKE \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_SMI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .smi = 1} + +/* End marker */ +#define GPIO_LIST_END 0xffffffff + +#define GPIO_END \ + { .pad_conf0 = GPIO_LIST_END } + +/* Common default GPIO settings */ +#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K +#define GPIO_INPUT_PD GPIO_INPUT_PD_10K +#define GPIO_NC GPIO_INPUT_PU_10K +#define GPIO_DEFAULT GPIO_FUNC0 + +/* 16 DirectIRQs per supported bank */ +#define GPIO_MAX_DIRQS 16 + +/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO + * function 1. Indicate first / last GPIOs with function 1. */ +#define GPIO_NONE 255 +/* All NCORE GPIOs are function 0 */ +#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE +#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE +/* SCORE GPIO [92:93] are function 1 */ +#define GPSCORE_GPIO_F1_RANGE_START 92 +#define GPSCORE_GPIO_F1_RANGE_END 93 +/* SSUS GPIO [11:21] are function 1 */ +#define GPSSUS_GPIO_F1_RANGE_START 11 +#define GPSSUS_GPIO_F1_RANGE_END 21 + +struct soc_gpio_map { + u32 pad_conf0; + u32 pad_conf1; + u32 pad_val; + u32 use_sel : 1; + u32 io_sel : 1; + u32 gp_lvl : 1; + u32 tpe : 1; + u32 tne : 1; + u32 wake_en : 1; + u32 smi : 1; + u32 is_gpio : 1; + u32 sci : 1; +} __attribute__ ((packed)); + +struct soc_gpio_config { + const struct soc_gpio_map *ncore; + const struct soc_gpio_map *score; + const struct soc_gpio_map *ssus; + const u8 (*core_dirq)[GPIO_MAX_DIRQS]; + const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; +}; + +/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +struct gpio_bank { + const int gpio_count; + const u8* gpio_to_pad; + const int legacy_base; + const unsigned long pad_base; + const u8 has_wake_en :1; + const u8 gpio_f1_range_start; + const u8 gpio_f1_range_end; +}; + +void setup_soc_gpios(struct soc_gpio_config *config); +/* This function is weak and can be overridden by a mainboard function. */ +struct soc_gpio_config* mainboard_get_gpios(void); + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 + +static inline unsigned int score_pconf0(int pad_num) +{ + return GPSCORE_PAD_BASE + pad_num * 16; +} + +static inline unsigned int ssus_pconf0(int pad_num) +{ + return GPSSUS_PAD_BASE + pad_num * 16; +} + +static inline void score_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = score_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + write32(pconf0_addr, reg); +} + +static inline void ssus_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = ssus_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + write32(pconf0_addr, reg); +} + +/* These functions require that the input pad be configured as an input GPIO */ +static inline int score_get_gpio(int pad) +{ + uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG; + + return read32(val_addr) & PAD_VAL_HIGH; +} + +static inline int ssus_get_gpio(int pad) +{ + uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG; + + return read32(val_addr) & PAD_VAL_HIGH; +} + +static inline void ssus_disable_internal_pull(int pad) +{ + const uint32_t pull_mask = ~(0xf << 7); + write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); +} + +#endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/iomap.h b/src/soc/intel/fsp_baytrail/baytrail/iomap.h new file mode 100644 index 0000000..867484b --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/iomap.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IOMAP_H_ +#define _BAYTRAIL_IOMAP_H_ + + +/* + * Memory Mapped IO bases. + */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + +/* + * IO Port bases. + */ +#define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#ifndef __ACPI__ +/* Read Top of Low Memory (BMBOUND) */ +uint32_t nc_read_top_of_low_memory(void); +#endif + +#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/iosf.h b/src/soc/intel/fsp_baytrail/baytrail/iosf.h new file mode 100644 index 0000000..8fd1e24 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/iosf.h @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IOSF_H_ +#define _BAYTRAIL_IOSF_H_ + +#include <stdint.h> +#include <baytrail/pci_devs.h> + +/* + * The Bay Trail SoC has a message network called IOSF Sideband. The access + * routines are through 3 registers in PCI config space of 00:00.0: + * MCR - control register + * MDR - data register + * MCRX - control register extension + * The extension register is only used for addresses that don't fit into the + * 8 bit register address. + */ + +#ifndef PCI_DEV +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) +#endif +#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) + +#define MCR_REG 0xd0 +#define IOSF_OPCODE(x) ((x) << 24) +#define IOSF_PORT(x) ((0xff & (x)) << 16) +#define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) (((~0xff) & (x))) +#define IOSF_BYTE_EN_0 0x10 +#define IOSF_BYTE_EN_1 0x20 +#define IOSF_BYTE_EN_2 0x40 +#define IOSF_BYTE_EN_3 0x80 +#define IOSF_BYTE_EN \ + (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) +#define MDR_REG 0xd4 +#define MCRX_REG 0xd8 + +uint32_t iosf_bunit_read(int reg); +void iosf_bunit_write(int reg, uint32_t val); +uint32_t iosf_dunit_read(int reg); +void iosf_dunit_write(int reg, uint32_t val); +/* Some registers are per channel while the gloals live in dunit 0 */ +uint32_t iosf_dunit_ch0_read(int reg); +uint32_t iosf_dunit_ch1_read(int reg); +uint32_t iosf_punit_read(int reg); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); + +/* IOSF ports. */ +#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ +#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ +#define IOSF_PORT_BUNIT 0x03 /* System Memroy Arbiter/Bunit */ +#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ + +/* Read and write opcodes differ per port. */ +#define IOSF_OP_READ_SYSMEMC 0x10 +#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) +#define IOSF_OP_READ_BUNIT 0x10 +#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) +#define IOSF_OP_READ_LPSS 0x06 +#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) + +/* + * BUNIT Registers. + */ + +#define BNOCACHE 0x23 +/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ +#define BUNIT_BMBOUND 0x25 +/* BMBOUND_HI describes the available ram above 4GiB. It has a + * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 + * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB + * granularity care needs to be taken with the e820 map to account for a hole + * in the ram. */ +#define BUNIT_BMBOUND_HI 0x26 +#define BUNIT_MMCONF_REG 0x27 +/* The SMMRR registers define the SMM region in MiB granularity. */ +#define BUNIT_SMRRL 0x2e +#define BUNIT_SMRRH 0x2f +# define BUNIT_SMRR_ENABLE (1 << 31) + +/* + * DUNIT Registers. + */ + +#define DRP 0x00 +# define DRP_DIMM0_RANK0_EN (0x01 << 0) +# define DRP_DIMM0_RANK1_EN (0x01 << 1) +# define DRP_DIMM1_RANK0_EN (0x01 << 2) +# define DRP_DIMM1_RANK1_EN (0x01 << 3) +# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ + DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) +#define DTR0 0x01 +# define DTR0_SPEED_MASK 0x03 +# define DTR0_SPEED_800 0x00 +# define DTR0_SPEED_1066 0x01 +# define DTR0_SPEED_1333 0x02 +# define DTR0_SPEED_1600 0x03 + + +/* + * LPSS Registers + */ +#define LPSS_SIO_DMA1_CTL 0x280 +#define LPSS_I2C1_CTL 0x288 +#define LPSS_I2C2_CTL 0x290 +#define LPSS_I2C3_CTL 0x298 +#define LPSS_I2C4_CTL 0x2a0 +#define LPSS_I2C5_CTL 0x2a8 +#define LPSS_I2C6_CTL 0x2b0 +#define LPSS_I2C7_CTL 0x2b8 +#define LPSS_SIO_DMA2_CTL 0x240 +#define LPSS_PWM1_CTL 0x248 +#define LPSS_PWM2_CTL 0x250 +#define LPSS_HSUART1_CTL 0x258 +#define LPSS_HSUART2_CTL 0x260 +#define LPSS_SPI_CTL 0x268 +# define LPSS_CTL_ACPI_INT_EN (1 << 21) +# define LPSS_CTL_PCI_CFG_DIS (1 << 20) +# define LPSS_CTL_SNOOP (1 << 18) +# define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) + +/* + * SCC Registers + */ +#define SCC_SD_CTL 0x504 +#define SCC_SDIO_CTL 0x508 +#define SCC_MMC_CTL 0x50c +# define SCC_CTL_PCI_CFG_DIS (1 << 0) +# define SCC_CTL_ACPI_INT_EN (1 << 1) + +/* + * CCU Registers + */ + +#define PLT_CLK_CTRL_0 0x3c +#define PLT_CLK_CTRL_1 0x40 +#define PLT_CLK_CTRL_2 0x44 +#define PLT_CLK_CTRL_3 0x48 +#define PLT_CLK_CTRL_4 0x4c +#define PLT_CLK_CTRL_5 0x50 +# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) +# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) +# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) + +/* + * USBPHY Registers + */ +#define USBPHY_COMPBG 0x7f04 +#define USBPHY_PER_PORT_LANE0 0x4100 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 +#define USBPHY_PER_PORT_LANE1 0x4200 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 +#define USBPHY_PER_PORT_LANE2 0x4300 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 +#define USBPHY_PER_PORT_LANE3 0x4400 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 + +/* + * USHPHY Registers + */ +#define USHPHY_CDN_PLL_CONTROL 0x03c0 +#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 +#define USHPHY_CCDRLF 0x8040 +#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 +#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 +#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 +#define USHPHY_REE_DAC_CONTROL 0x80b8 +#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 + +#endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/irq.h b/src/soc/intel/fsp_baytrail/baytrail/irq.h new file mode 100644 index 0000000..98ca116 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/irq.h @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 +/* The below IRQs are for when devices are in ACPI mode. Active low. */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +#define GPIO_NC_IRQ 48 +#define GPIO_SC_IRQ 49 +#define GPIO_SUS_IRQ 50 +/* GPIO direct / dedicated IRQs. */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00 +# define SCIS_MASK 0x07 +# define SCIS_IRQ9 0x00 +# define SCIS_IRQ10 0x01 +# define SCIS_IRQ11 0x02 +# define SCIS_IRQ20 0x04 +# define SCIS_IRQ21 0x05 +# define SCIS_IRQ22 0x06 +# define SCIS_IRQ23 0x07 + +/* In each mainboard directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + +#define NUM_OF_PCI_DEVS 32 +#define NUM_PIRQS 8 + +struct baytrail_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_OF_PCI_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct baytrail_irq_route global_baytrail_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct baytrail_irq_route global_baytrail_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/lpc.h b/src/soc/intel/fsp_baytrail/baytrail/lpc.h new file mode 100644 index 0000000..9dd0439 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/lpc.h @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_LPC_H_ +#define _BAYTRAIL_LPC_H_ + +#define FADT_SOC_LPC_DEV 0, PCI_DEVFN(0x1f,0) + +/* PCI config registers in LPC bridge. */ +#define REVID 0x08 +#define ABASE 0x40 /* IO BAR */ +#define PBASE 0x44 /* MEM BAR */ +#define GBASE 0x48 /* IO BAR */ +#define IOBASE 0x4c /* MEM BAR */ +#define IBASE 0x50 /* MEM BAR */ +#define SBASE 0x54 /* MEM BAR */ +#define MPBASE 0x58 /* MEM BAR */ +#define PUBASE 0x5c +#define SET_BAR_ENABLE 0x02 +#define UART_CONT 0x80 +#define RCBA 0xf0 +#define RCBA_ENABLE 0x01 + +#define ILB_ACTL 0 +#define ILB_MC 0x4 +#define ILB_PIRQA_ROUT 0x8 +#define ILB_PIRQB_ROUT 0x9 +#define ILB_PIRQC_ROUT 0xA +#define ILB_PIRQD_ROUT 0xB +#define ILB_PIRQE_ROUT 0xC +#define ILB_PIRQF_ROUT 0xD +#define ILB_PIRQG_ROUT 0xE +#define ILB_PIRQH_ROUT 0xF +#define ILB_SERIRQ_CNTL 0x10 +#define SCNT_CONTINUOUS_MODE (1 << 7) +#define SCNT_QUIET_MODE 0 +#define ILB_IR00 0x20 +#define ILB_IR01 0x22 +#define ILB_IR02 0x24 +#define ILB_IR03 0x26 +#define ILB_IR04 0x28 +#define ILB_IR05 0x2A +#define ILB_IR06 0x2C +#define ILB_IR07 0x2E +#define ILB_IR08 0x30 +#define ILB_IR09 0x32 +#define ILB_IR10 0x34 +#define ILB_IR11 0x36 +#define ILB_IR12 0x38 +#define ILB_IR13 0x3A +#define ILB_IR14 0x3C +#define ILB_IR15 0x3E +#define ILB_IR16 0x40 +#define ILB_IR17 0x42 +#define ILB_IR18 0x44 +#define ILB_IR19 0x46 +#define ILB_IR20 0x48 +#define ILB_IR21 0x4A +#define ILB_IR22 0x4C +#define ILB_IR23 0x4E +#define ILB_IR24 0x50 +#define ILB_IR25 0x52 +#define ILB_IR26 0x54 +#define ILB_IR27 0x56 +#define ILB_IR28 0x58 +#define ILB_IR29 0x5A +#define ILB_IR30 0x5C +#define ILB_IR31 0x5E +#define ILB_OIC 0x60 +#define SIRQEN (1 << 12) +#define AEN (1 << 8) + +#define RID_A_STEPPING_START 1 +#define RID_B_STEPPING_START 5 +#define RID_C_STEPPING_START 0xe +enum baytrail_stepping { + STEP_A0, + STEP_A1, + STEP_B0, + STEP_B1, + STEP_B2, + STEP_B3, + STEP_C0, +}; + +/* Registers behind the RCBA_BASE_ADDRESS bar. */ +#define GCS 0x00 +# define BILD (1 << 0) + +/* Default IO range claimed by the LPC devices. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 +#define IO_APIC_RANGE_SIZE 0x1000 + +#endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/msr.h b/src/soc/intel/fsp_baytrail/baytrail/msr.h new file mode 100644 index 0000000..882346c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/msr.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_MSR_H_ +#define _BAYTRAIL_MSR_H_ + +#define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_POWER_MISC 0x120 +#define MSR_IA32_PERF_CTL 0x199 +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_POWER_CTL 0x1fc +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_TURBO_RATIOS 0x66c +#define MSR_IACORE_VIDS 0x66b +#define MSR_IACORE_TURBO_VIDS 0x66d + +/* Read BCLK from MSR */ +unsigned bus_freq_khz(void); + +#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvm.h b/src/soc/intel/fsp_baytrail/baytrail/nvm.h new file mode 100644 index 0000000..d0cbf7b --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/nvm.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NVM_H_ +#define _NVM_H_ + +#include <stddef.h> + +/* Determine if area is erased. returns 1 if erased. 0 otherwise. */ +int nvm_is_erased(const void *start, size_t size); + +/* Erase region according to start and size. Returns < 0 on error else 0. */ +int nvm_erase(void *start, size_t size); + +/* Write data to NVM. Returns 0 on success < 0 on error. */ +int nvm_write(void *start, const void *data, size_t size); + +#endif /* _NVM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h new file mode 100644 index 0000000..1e12310 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_NVS_H_ +#define _BAYTRAIL_NVS_H_ + +#include <baytrail/device_nvs.h> + +typedef struct { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 pcnt; /* 0x11 - Processor Count */ + u8 tpmp; /* 0x12 - TPM Present and Enabled */ + u8 tlvl; /* 0x13 - Throttle Level */ + u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ + u8 rsvd1[11]; + + /* Device Config */ + u8 s5u0; /* 0x20 - Enable USB0 in S5 */ + u8 s5u1; /* 0x21 - Enable USB1 in S5 */ + u8 s3u0; /* 0x22 - Enable USB0 in S3 */ + u8 s3u1; /* 0x23 - Enable USB1 in S3 */ + u8 tact; /* 0x24 - Thermal Active trip point */ + u8 tpsv; /* 0x25 - Thermal Passive trip point */ + u8 tcrt; /* 0x26 - Thermal Critical trip point */ + u8 dpte; /* 0x27 - Enable DPTF */ + u8 rsvd2[8]; + + /* Base Addresses */ + u32 cmem; /* 0x30 - CBMEM TOC */ + u32 tolm; /* 0x34 - Top of Low Memory */ + u32 cbmc; /* 0x38 - coreboot memconsole */ + u8 rsvd3[196]; + + /* Baytrail LPSS (0x1000) */ + device_nvs_t dev; +} __attribute__((packed)) global_nvs_t; + +#ifdef __SMM__ +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); +#endif + +#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/pattrs.h b/src/soc/intel/fsp_baytrail/baytrail/pattrs.h new file mode 100644 index 0000000..d4eb721 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/pattrs.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PATTRS_H_ +#define _PATTRS_H_ + +#include <stdint.h> +#include <cpu/x86/msr.h> + +enum { + IACORE_MIN, + IACORE_LFM, + IACORE_MAX, + IACORE_TURBO, + IACORE_END +}; + +/* The pattrs structure is a common place to stash pertinent information + * about the processor or platform. Instead of going to the source (msrs, cpuid) + * every time an attribute is needed use the pattrs structure. + */ +struct pattrs { + msr_t platform_id; + msr_t platform_info; + int iacore_ratios[IACORE_END]; + int iacore_vids[IACORE_END]; + uint32_t cpuid; + int revid; + int stepping; + const void *microcode_patch; + int address_bits; + int num_cpus; + unsigned bclk_khz; +}; + +/* This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. */ +#define PATTRS_GLOB_NAME __global_pattrs +#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME +extern DEFINE_PATTRS; + +static inline const struct pattrs *pattrs_get(void) +{ + return &PATTRS_GLOB_NAME; +} + + +#endif /* _PATTRS_H_ */ + diff --git a/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h b/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h new file mode 100644 index 0000000..dc41d13 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PCI_DEVS_H_ +#define _BAYTRAIL_PCI_DEVS_H_ + +#define BUS0 0 + +/* All these devices live on bus 0 with the associated device and function */ +#define DEV_FUNC(x,y) ((x<<3) | y) + + +/* SoC transaction router */ +#define SOC_DEV 0x0 +#define SOC_FUNC 0 +# define SOC_DEVID 0x0f00 +# define SOC_DEV_FUNC DEV_FUNC(SOC_DEV,SOC_FUNC) + + +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +# define GFX_DEVID 0x0f31 +# define GFX_DEV_FUNC DEV_FUNC(GFX_DEV,GFX_FUNC) + +/* MIPI */ +#define MIPI_DEV 0x3 +#define MIPI_FUNC 0 +# define MIPI_DEVID 0x0f38 +# define MIPI_DEV_FUNC DEV_FUNC(MIPI_DEV,MIPI_FUNC) + + +/* SDIO Port */ +#define EMMC_DEV 0x10 +#define EMMC_FUNC 0 +# define EMMC_DEVID 0x0f14 +# define EMMC_DEV_FUNC DEV_FUNC(EMMC_DEV,EMMC_FUNC) + +/* SDIO Port */ +#define SDIO_DEV 0x11 +#define SDIO_FUNC 0 +# define SDIO_DEVID 0x0f15 +# define SDIO_DEV_FUNC DEV_FUNC(SDIO_DEV,SDIO_FUNC) + +/* SD Port */ +#define SD_DEV 0x12 +#define SD_FUNC 0 +# define SD_DEVID 0x0f16 +# define SD_DEV_FUNC DEV_FUNC(SD_DEV,SD_FUNC) + +/* SATA */ +#define SATA_DEV 0x13 +#define SATA_FUNC 0 +# define IDE1_DEVID 0x0f20 +# define IDE2_DEVID 0x0f21 +# define AHCI1_DEVID 0x0f22 +# define AHCI2_DEVID 0x0f23 +# define SATA_MA 0x84 +# define SATA_MAP 0x90 +# define SATA_PSC 0x92 +# define SATA_SP 0xD0 +# define SATA_BIST1 0xE4 +# define SATA_BIST2 0xE8 +# define SATA_DEV_FUNC DEV_FUNC(SATA_DEV,SATA_FUNC) + +#define SATA_MA_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_MA +#define SATA_SP_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_SP +#define SATA_BIST1_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST1 +#define SATA_BIST2_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST2 + +/* xHCI */ +#define XHCI_DEV 0x14 +#define XHCI_FUNC 0 +# define XHCI_DEVID 0x0f35 +# define XHCI_FUS_REG 0xE0 +# define XHCI_FUNC_DISABLE (1 << 0) +# define XHCI_USB2PR_REG 0xD0 +# define XHCI_DEV_FUNC DEV_FUNC(XHCI_DEV,XHCI_FUNC) + +/* LPE Audio */ +#define LPE_DEV 0x15 +#define LPE_FUNC 0 +# define LPE_DEVID 0x0f28 +# define LPE_DEV_FUNC DEV_FUNC(LPE_DEV,LPE_FUNC) + +/* OTG */ +#define OTG_DEV 0x16 +#define OTG_FUNC 0 +# define OTG_DEVID 0x0f37 +# define OTG_DEV_FUNC DEV_FUNC(LPE_DEV,LPE_FUNC) + +/* MMC Port */ +#define MMC45_DEV 0x17 +#define MMC45_FUNC 0 +# define MMC45_DEVID 0x0f50 +# define MMC45_DEV_FUNC DEV_FUNC(MMC45_DEV,MMC45_FUNC) + +/* Serial IO 1 */ +#define SIO1_DEV 0x18 +# define SIO_DMA1_DEV SIO1_DEV +# define SIO_DMA1_FUNC 0 +# define SIO_DMA1_DEVID 0x0f40 +# define I2C1_DEV SIO1_DEV +# define I2C1_FUNC 1 +# define I2C1_DEVID 0x0f41 +# define I2C2_DEV SIO1_DEV +# define I2C2_FUNC 2 +# define I2C2_DEVID 0x0f42 +# define I2C3_DEV SIO1_DEV +# define I2C3_FUNC 3 +# define I2C3_DEVID 0x0f43 +# define I2C4_DEV SIO1_DEV +# define I2C4_FUNC 4 +# define I2C4_DEVID 0x0f44 +# define I2C5_DEV SIO1_DEV +# define I2C5_FUNC 5 +# define I2C5_DEVID 0x0f45 +# define I2C6_DEV SIO1_DEV +# define I2C6_FUNC 6 +# define I2C6_DEVID 0x0f46 +# define I2C7_DEV SIO1_DEV +# define I2C7_FUNC 7 +# define I2C7_DEVID 0x0f47 +# define SIO_DMA1_DEV_FUNC DEV_FUNC(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define I2C1_DEV_FUNC DEV_FUNC(I2C1_DEV,I2C1_FUNC) +# define I2C2_DEV_FUNC DEV_FUNC(I2C2_DEV,I2C2_FUNC) +# define I2C3_DEV_FUNC DEV_FUNC(I2C3_DEV,I2C3_FUNC) +# define I2C4_DEV_FUNC DEV_FUNC(I2C4_DEV,I2C4_FUNC) +# define I2C5_DEV_FUNC DEV_FUNC(I2C5_DEV,I2C5_FUNC) +# define I2C6_DEV_FUNC DEV_FUNC(I2C6_DEV,I2C6_FUNC) +# define I2C7_DEV_FUNC DEV_FUNC(I2C7_DEV,I2C7_FUNC) + +/* Trusted Execution Engine */ +#define TXE_DEV 0x1a +#define TXE_FUNC 0 +# define TXE_DEVID 0x0f18 +# define TXE_DEV_FUNC DEV_FUNC(TXE_DEV,TXE_FUNC) + +/* HD Audio */ +#define HDA_DEV 0x1b +#define HDA_FUNC 0 +# define HDA_DEVID 0x0f04 +# define HDA_DEV_FUNC DEV_FUNC(HDA_DEV,HDA_FUNC) +# define HDA_AZUBAR 0x14 +# define HDA_MMLA 0x64 +# define HDA_MMUA 0x68 +#define HDA_AZUBAR_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_AZUBAR +#define HDA_MMLA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMLA +#define HDA_MMUA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMUA + +/* PCIe Ports */ +#define PCIE_DEV 0x1c +# define PCIE_PORT1_DEV PCIE_DEV +# define PCIE_PORT1_FUNC 0 +# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV +# define PCIE_PORT2_FUNC 1 +# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV +# define PCIE_PORT3_FUNC 2 +# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV +# define PCIE_PORT4_FUNC 3 +# define PCIE_PORT4_DEVID 0x0f4e +# define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +# define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT2_FUNC) +# define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT3_FUNC) +# define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT4_FUNC) + +/* EHCI */ +#define EHCI_DEV 0x1d +#define EHCI_FUNC 0 +# define EHCI_DEVID 0x0f34 +# define EHCI_DEV_FUNC DEV_FUNC(EHCI_DEV,EHCI_FUNC) + +/* Serial IO 2 */ +#define SIO2_DEV 0x1e +# define SIO_DMA2_DEV SIO2_DEV +# define SIO_DMA2_FUNC 0 +# define SIO_DMA2_DEVID 0x0f06 +# define PWM1_DEV SIO2_DEV +# define PWM1_FUNC 1 +# define PWM1_DEVID 0x0f08 +# define PWM2_DEV SIO2_DEV +# define PWM2_FUNC 2 +# define PWM2_DEVID 0x0f09 +# define HSUART1_DEV SIO2_DEV +# define HSUART1_FUNC 3 +# define HSUART1_DEVID 0x0f0a +# define HSUART2_DEV SIO2_DEV +# define HSUART2_FUNC 4 +# define HSUART2_DEVID 0x0f0c +# define SPI_DEV SIO2_DEV +# define SPI_FUNC 5 +# define SPI_DEVID 0xf0e +# define SIO_DMA2_DEV_FUNC DEV_FUNC(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define PWM1_DEV_FUNC DEV_FUNC(PWM1_DEV,PWM1_FUNC) +# define PWM2_DEV_FUNC DEV_FUNC(PWM2_DEV,PWM2_FUNC) +# define HSUART1_DEV_FUNC DEV_FUNC(HSUART1_DEV,HSUART1_FUNC) +# define HSUART2_DEV_FUNC DEV_FUNC(HSUART2_DEV,HSUART2_FUNC) +# define SPI_DEV_FUNC DEV_FUNC(SPI_DEV,SPI_FUNC) + + +/* Platform Controller Unit */ +#define PCU_DEV 0x1f +# define LPC_DEV PCU_DEV +# define LPC_FUNC 0 +# define LPC_DEVID 0x0f1c +# define SMBUS_DEV PCU_DEV +# define SMBUS_FUNC 3 +# define SMBUS_DEVID 0x0f12 +# define LPC_DEV_FUNC DEV_FUNC(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) +# define SMBUS_DEV_FUNC DEV_FUNC(SMBUS_DEV,SMBUS_FUNC) + +#define INITIAL_TIMESTAMP_LOCATION HDA_MMUA_BDFO +#define BEFORE_CAR_TIMESTAMP_LOCATION SATA_BIST1_BDFO +#define ASM_BEFORE_CAR_TSC_LOC 0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST1 +#define AFTER_CAR_TIMESTAMP_LOCATION SATA_BIST2_BDFO +#define ASM_AFTER_CAR_TSC_LOC 0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST2 +#define START_ROMSTAGE_TIMESTAMP_LOCATION HDA_MMLA_BDFO +#define BEFORE_RAMINIT_TIMESTAMP_LOCATION SATA_MA_BDFO + +#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/pcie.h b/src/soc/intel/fsp_baytrail/baytrail/pcie.h new file mode 100644 index 0000000..98effea --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/pcie.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PCIE_H_ +#define _BAYTRAIL_PCIE_H_ + +/* PCIe root port config space registers. */ +#define XCAP 0x40 +# define SI (1 << 24) +#define DCAP 0x44 +# define MPS_MASK 0x7 +#define DCTL_DSTS 0x48 +# define URE (1 << 3) +# define FEE (1 << 2) +# define NFE (1 << 1) +# define CEE (1 << 0) +#define LCAP 0x4c +# define L1EXIT_SHIFT 15 +# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) +#define LCTL 0x50 +# define CCC (1 << 6) +# define RL (1 << 5) +# define LD (1 << 4) +#define LSTS 0x52 +#define SLCAP 0x54 +# define SLN_SHIFT 19 +# define SLS_SHIFT 15 +# define SLV_SHIFT 7 +# define HPC (1 << 6) +# define HPS (1 << 5) +#define SLCTL_SLSTS 0x58 +# define PDS (1 << 22) +#define DCAP2 0x64 +# define OBFFS (0x3 << 18) +# define LTRMS (1 << 11) +#define DSTS2 0x68 +# define OBFFEN (3 << 13) +# define LTRME (1 << 10) +# define CTD (1 << 4) +#define CHCFG 0xd0 +# define UPSD (1 << 24) +# define UNRS (1 << 15) +# define UPRS (1 << 14) +#define MPC2 0xd4 +# define IPF (1 << 11) +# define LSTP (1 << 6) +# define EOIFD (1 << 1) +#define MPC 0xd8 +# define CCEL_SHIFT 15 +# define CCEL_MASK (0x7 << CCEL_SHIFT) +#define RPPGEN 0xe0 +# define RPSCGEN (1 << 15) +# define LCLKREQEN (1 << 13) +# define BBCLKREQEN (1 << 12) +# define SRDLCGEN (1 << 11) +# define SRDBCGEN (1 << 10) +# define RPDLCGEN (1 << 9) +# define RPDBCGEN (1 << 8) +#define PWRCTL 0xe8 +# define RPL1SQPOL (1 << 1) +# define RPDTSQPOL (1 << 0) +#define PHYCTL2_IOSFBCTL 0xf4 +# define PLL_OFF_EN (1 << 8) +# define TDFT (3 << 14) +# define TXCFGCHWAIT (3 << 12) +# define SIID (3 << 26) +#define STRPFUSECFG 0xfc +# define LANECFG_SHIFT 14 +# define LANECFG_MASK (0x3 << LANECFG_SHIFT) +#define AERCH 0x100 +#define NFTS 0x314 +#define L0SC 0x318 +#define CFG2 0x320 +# define CSREN (1 << 22) +# define LATGC_SHIFT 6 +# define LATGC_MASK (0x7 << LATGC_SHIFT) +#define PCIEDBG 0x324 +# define SPCE (1 << 5) +#define PCIESTS1 0x328 +#define PCIEALC 0x338 +#define RTP 0x33c +#define PHYCTL4 0x408 +# define SQDIS (1 << 27) + + +#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/pmc.h b/src/soc/intel/fsp_baytrail/baytrail/pmc.h new file mode 100644 index 0000000..ee15dd9 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/pmc.h @@ -0,0 +1,307 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PMC_H_ +#define _BAYTRAIL_PMC_H_ + + +#define IOCOM1 0x3f8 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) +#define GEN_PMCON1 0x20 +# define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) +# define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) +# define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define MMC45_DIS (1 << 8) +# define EMMC_DIS (1 << 8) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MIPI_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) +#define GPIO_ROUT 0x58 +# define ROUTE_MASK 3 +# define ROUTE_NONE 0 +# define ROUTE_SMI 1 +# define ROUTE_SCI 2 +#define PLT_CLK_CTL_0 0x60 +#define PLT_CLK_CTL_1 0x64 +#define PLT_CLK_CTL_2 0x68 +#define PLT_CLK_CTL_3 0x6c +#define PLT_CLK_CTL_4 0x70 +#define PLT_CLK_CTL_5 0x74 +# define CLK_FREQ_25MHZ (0x0 << 2) +# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_CTL_D3_LPE (0x0 << 0) +# define CLK_CTL_ON (0x1 << 0) +# define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define CORE_GPIO_STS7 (1 << 31) +#define CORE_GPIO_STS6 (1 << 30) +#define CORE_GPIO_STS5 (1 << 29) +#define CORE_GPIO_STS4 (1 << 28) +#define CORE_GPIO_STS3 (1 << 27) +#define CORE_GPIO_STS2 (1 << 26) +#define CORE_GPIO_STS1 (1 << 25) +#define CORE_GPIO_STS0 (1 << 24) +#define SUS_GPIO_STS7 (1 << 23) +#define SUS_GPIO_STS6 (1 << 22) +#define SUS_GPIO_STS5 (1 << 21) +#define SUS_GPIO_STS4 (1 << 20) +#define SUS_GPIO_STS3 (1 << 19) +#define SUS_GPIO_STS2 (1 << 18) +#define SUS_GPIO_STS1 (1 << 17) +#define SUS_GPIO_STS0 (1 << 16) +#define PME_B0_STS_BIT 13 +#define PME_B0_STS (1 << PME_B0_STS_BIT) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define PCIE_WAKE3_STS (1 << 8) +#define PCIE_WAKE2_STS (1 << 7) +#define PCIE_WAKE1_STS (1 << 6) +#define GUNIT_SCI_STS (1 << 5) +#define PUNIT_SCI_STS (1 << 4) +#define PCIE_WAKE0_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define CORE_GPIO_EN7 (1 << 31) +#define CORE_GPIO_EN6 (1 << 30) +#define CORE_GPIO_EN5 (1 << 29) +#define CORE_GPIO_EN4 (1 << 28) +#define CORE_GPIO_EN3 (1 << 27) +#define CORE_GPIO_EN2 (1 << 26) +#define CORE_GPIO_EN1 (1 << 25) +#define CORE_GPIO_EN0 (1 << 24) +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) +#define PME_B0_EN (1 << 13) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define PCIE_WAKE3_EN (1 << 8) +#define PCIE_WAKE2_EN (1 << 7) +#define PCIE_WAKE1_EN (1 << 6) +#define PCIE_WAKE0_EN (1 << 3) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define USB_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +/* I/O ports */ +#define RST_CNT 0xcf9 +# define FULL_RST (1 << 3) +# define RST_CPU (1 << 2) +# define SYS_RST (1 << 1) + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; +} __attribute__((packed)); + +/* Power Management Utility Functions. */ +uint16_t get_pmbase(void); +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); + +#if IS_ENABLED(CONFIG_ELOG) +void southcluster_log_state(void); +#else +static inline void southcluster_log_state(void) {} +#endif + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h new file mode 100644 index 0000000..095f09c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RAMSTAGE_H_ +#define _BAYTRAIL_RAMSTAGE_H_ + +#include <device/device.h> + +/* The baytrail_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. */ +void baytrail_init_pre_device(void); +void baytrail_init_cpus(device_t dev); +void set_max_freq(void); +void southcluster_enable_dev(device_t dev); +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); + +extern struct pci_operations soc_pci_ops; + +#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/reset.h b/src/soc/intel/fsp_baytrail/baytrail/reset.h new file mode 100644 index 0000000..dbf0fd2 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/reset.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RESET_H_ +#define _BAYTRAIL_RESET_H_ +#include <reset.h> + +/* Bay Trail has the following types of resets: + * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 + * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 + * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 + * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 + * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but + * with ETR[20] set. + */ + +void cold_reset(void); +void warm_reset(void); + +#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/romstage.h b/src/soc/intel/fsp_baytrail/baytrail/romstage.h new file mode 100644 index 0000000..8feab8a --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/romstage.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_ROMSTAGE_H_ +#define _BAYTRAIL_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +void report_platform_info(void); + +#include <stdint.h> +#include <arch/cpu.h> + +#include <fsptypes.h> + +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); + +#define NUM_ROMSTAGE_TS 4 + +void tco_disable(void); +void punit_init(void); +void set_max_freq(void); +void early_mainboard_romstage_entry(void); +void late_mainboard_romstage_entry(void); +void get_func_disables(uint32_t *mask, uint32_t *mask2); + +#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) +void byt_config_com1_and_enable(void); +#else +static inline void byt_config_com1_and_enable(void) { } +#endif + +#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h new file mode 100644 index 0000000..0208c9f --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_SMM_H_ +#define _BAYTRAIL_SMM_H_ + +/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig + * is included after chipset code. This causes the chipset's Kconfig to be + * clobbered by the arch/x86/Kconfig if they have the same name. */ +static inline int smm_region_size(void) +{ +#ifndef CONFIG_SMM_TSEG_SIZE +#error CONFIG_SMM_TSEG_SIZE must be set. +#endif + + /* Make it 8MiB by default. */ + if (CONFIG_SMM_TSEG_SIZE == 0) + return (8 << 20); + return CONFIG_SMM_TSEG_SIZE; +} + +void *smm_region_start(void); + +#if !defined(__PRE_RAM__) && !defined(__SMM___) +#include <stdint.h> +void southcluster_smm_clear_state(void); +void southcluster_smm_enable_smi(void); +void southcluster_smm_save_gpio_route(uint32_t route); +#endif + +#endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/spi.h b/src/soc/intel/fsp_baytrail/baytrail/spi.h new file mode 100644 index 0000000..ee1648a --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/spi.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_SPI_H_ +#define _BAYTRAIL_SPI_H_ + +#include <stdint.h> + +/* These registers live behind SPI_BASE_ADDRESS. */ +#define HSFSTS 0x04 +# define FLOCKDN (0x1 << 15) +#define PREOP 0x94 +#define OPTYPE 0x96 +#define OPMENU0 0x98 +#define OPMENU1 0x9c +#define LVSCC 0xc4 +# define VCL (0x1 << 23) +# define EO(x) (((x) & 0xff) << 8) +# define WG_1_BYTE (0x0 << 2) +# define WG_64_BYTE (0x1 << 2) +# define BES_256_BYTE (0x0 << 0) +# define BES_4_KB (0x1 << 0) +# define BES_8_KB (0x2 << 0) +# define BES_64_KB (0x3 << 0) +#define UVSCC 0xc8 +#define SCS 0xf8 +# define SMIWPEN (0x1 << 7) +#define BCR 0xfc +# define EISS (0x1 << 5) +# define SRC_MASK (0x3 << 2) +# define SRC_CACHE_NO_PREFETCH (0x0 << 2) +# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) +# define SRC_CACHE_PREFETCH (0x2 << 2) +# define BCR_LE (0x1 << 1) +# define BCR_WPD (0x1 << 0) + +/* + * SPI lockdown configuration. + */ +struct spi_config { + uint16_t preop; + uint16_t optype; + uint32_t opmenu[2]; + uint32_t lvscc; + uint32_t uvscc; +}; + +/* Return 0 on success < 0 on failure. */ +int mainboard_get_spi_config(struct spi_config *cfg); + +#endif /* _BAYTRAIL_SPI_H_ */ + diff --git a/src/soc/intel/fsp_baytrail/baytrail/xhci.h b/src/soc/intel/fsp_baytrail/baytrail/xhci.h new file mode 100644 index 0000000..b317361 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/xhci.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_XHCI_H +#define BAYTRAIL_XHCI_H + +/* XHCI PCI Registers */ +#define XHCI_PWR_CTL_STS 0x74 +#define XHCI_USB2PR 0xd0 +#define XHCI_USB2PRM 0xd4 +#define XHCI_USB3PR 0xd8 +#define XHCI_USB3PRM 0xdc +#define XHCI_USB2PDO 0xe4 +#define XHCI_USB3PDO 0xe8 + +/* XHCI Memory Registers */ +#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10)) +# define XHCI_USB3_PORTSC_CHST (0x7f << 17) +# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ + +/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ +#define BYTM_USB2_PORT_COUNT 4 +#define BYTM_USB2_PORT_MAP 0xf +#define BYTM_USB3_PORT_COUNT 1 +#define BYTM_USB3_PORT_MAP 0x1 + +#define XHCI_RESET_TIMEOUT 100000 /* 100ms */ + +#endif /* BAYTRAIL_XHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c new file mode 100644 index 0000000..1623f04 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/spi.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <reset.h> + +/* + * check for a warm reset and do a hard reset instead. + */ +static void check_for_warm_reset(void) +{ + + /* + * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. + * If either is true, then this is a warm reset so execute a Hard Reset + */ + if ( (inb(0xcf9) == 0x04) || + (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) { + outb(0x00, 0xcf9); + outb(0x06, 0xcf9); + } +} + +static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +{ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(void) +{ + uint32_t bcr = SPI_BASE_ADDRESS + BCR; + /* Enable caching and prefetching in the SPI controller. */ + write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); +} + +static void enable_rom_caching(void) +{ + msr_t msr; + + disable_cache(); + set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, + CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + enable_cache(); + + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRRdefType_MSR, msr); +} + +static void setup_mmconfig(void) +{ + uint32_t reg; + + /* Set up the MMCONF range. The register lives in the BUNIT. The + * IO variant of the config access needs to be used initially to + * properly configure as the IOSF access registers live in PCI + * config space. */ + reg = 0; + /* Clear the extended register. */ + pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | + IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; + pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} + +static void bootblock_cpu_init(void) +{ + + check_for_warm_reset(); + + /* Allow memory-mapped PCI config access. */ + setup_mmconfig(); + enable_rom_caching(); + enable_spi_prefetch(); +} diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c new file mode 100644 index 0000000..839e8dc --- /dev/null +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <drivers/intel/fsp/fsp_util.h> +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static void finalize_dev (device_t dev) +{ + /* + * Notify FSP for PostPciEnumeration. + * Northbridge APIC init should be early and late enough... + */ + printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); + FspNotify(EnumInitPhaseAfterPciEnumeration); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .final = &finalize_dev, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void cpu_bus_noop(device_t dev) { } + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = baytrail_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", + dev_name(dev), dev->path.type); + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } + } +} + +static void finalize_chip(void *chip_info) +{ + /* Notify FSP for ReadyToBoot */ + printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); + FspNotify(EnumInitPhaseReadyToBoot); + +} + +/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ +static void soc_init(void *chip_info) +{ + baytrail_init_pre_device(); +} + +struct chip_operations soc_intel_fsp_baytrail_ops = { + CHIP_NAME("Intel BayTrail SoC") + .enable_dev = enable_dev, + .init = soc_init, + .final = &finalize_chip, +}; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_set_subsystem, +}; diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h new file mode 100644 index 0000000..394c0f3 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _FSP_BAYTRAIL_CHIP_H_ +#define _FSP_BAYTRAIL_CHIP_H_ + +#include <arch/acpi.h> + +/* The devicetree parser expects chip.h to reside directly in the path + * specified by the devicetree. */ + +struct soc_intel_fsp_baytrail_config { + + /* VR low power settings -- enable PS2 mode for gfx and core */ + int vnn_ps2_enable; + int vcc_ps2_enable; + + /* USB Port Disable mask */ + uint16_t usb2_port_disable_mask; + uint16_t usb3_port_disable_mask; + + /* USB routing */ + int usb_route_to_xhci; + + /* USB PHY settings specific to the board */ + uint32_t usb2_per_port_lane0; + uint32_t usb2_per_port_rcomp_hs_pullup0; + uint32_t usb2_per_port_lane1; + uint32_t usb2_per_port_rcomp_hs_pullup1; + uint32_t usb2_per_port_lane2; + uint32_t usb2_per_port_rcomp_hs_pullup2; + uint32_t usb2_per_port_lane3; + uint32_t usb2_per_port_rcomp_hs_pullup3; + + /* LPE Audio Clock configuration. */ + int lpe_codec_clk_freq; /* 19 or 25 are valid. */ + int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + + /* Native SD Card controller - override controller capabilities. */ + uint32_t sdcard_cap_low; + uint32_t sdcard_cap_high; + +/* ***** UPD Configuration ***** */ + + /* Spd addresses */ + uint8_t MrcInitSPDAddr1; + uint8_t MrcInitSPDAddr2; + #define SPD_ADDR_DEFAULT 0x00 + #define SPD_ADDR_DISABLED 0xFF + + /* SataMode + * NOTE: These are offset by 1 to set 0 as "use default". This is so that + * if the register value is not set in the devicetree.cb file, the default + * value gets used. This is fixed up in the chipset_fsp_util.c code. + * + * 0x0 "IDE" + * 0x1 "AHCI" + */ + uint8_t SataMode; + #define SATA_MODE_DEFAULT 0x00 + #define SATA_MODE_IDE 0x01 + #define SATA_MODE_AHCI 0x02 + + /* + * MrcInitTsegSize + * 0x01, "1 MB" + * 0x02, "2 MB" + * 0x04, "4 MB" + * 0x08, "8 MB" + */ + uint16_t MrcInitTsegSize; + #define TSEG_SIZE_DEFAULT 0 + #define TSEG_SIZE_1_MB 1 + #define TSEG_SIZE_2_MB 2 + #define TSEG_SIZE_4_MB 4 + #define TSEG_SIZE_8_MB 8 + + /* + * MrcInitMmioSize + * 0x400, "1.0 GB"s + * 0x600, "1.5 GB" + * 0x800, "2.0 GB" + */ + uint16_t MrcInitMmioSize; + #define MMIO_SIZE_DEFAULT 0x00 + #define MMIO_SIZE_1_0_GB 0x400 + #define MMIO_SIZE_1_5_GB 0x600 + #define MMIO_SIZE_2_0_GB 0x800 + + /* + * eMMCBootMode + * NOTE: These are offset by 1 to set 0 as "use default". This is so that + * if the register value is not set in the devicetree.cb file, the default + * value gets used. This is fixed up in the chipset_fsp_util.c code + * + * 0x0 "Disabled" + * 0x1 "Auto" + * 0x2 "eMMC 4.1" + * 0x3 "eMMC 4.5" + */ + uint8_t eMMCBootMode; + #define EMMC_USE_DEFAULT 0 + #define EMMC_DISABLED 1 + #define EMMC_AUTO 2 + #define EMMC_4_1 3 + #define EMMC_4_5 4 + #define EMMC_FOLLOWS_DEVICETREE 5 + + /* + * IgdDvmt50PreAlloc + * 0x01, "32 MB" + * 0x02, "64 MB" + * 0x03, "96 MB" + * 0x04, "128 MB" + * 0x05, "160 MB" + * 0x06, "192 MB" + * 0x07, "224 MB" + * 0x08, "256 MB" + * 0x09, "288 MB" + * 0x0A, "320 MB" + * 0x0B, "352 MB" + * 0x0C, "384 MB" + * 0x0D, "416 MB" + * 0x0E, "448 MB" + * 0x0F, "480 MB" + * 0x10, "512 MB" + */ + uint8_t IgdDvmt50PreAlloc; + #define IGD_MEMSIZE_DEFAULT 0x00 + #define IGD_MEMSIZE_32MB 0x01 + #define IGD_MEMSIZE_64MB 0x02 + #define IGD_MEMSIZE_96MB 0x03 + #define IGD_MEMSIZE_128MB 0x04 + #define IGD_MEMSIZE_160MB 0x05 + #define IGD_MEMSIZE_192MB 0x06 + #define IGD_MEMSIZE_224MB 0x07 + #define IGD_MEMSIZE_256MB 0x08 + #define IGD_MEMSIZE_288MB 0x09 + #define IGD_MEMSIZE_320MB 0x0A + #define IGD_MEMSIZE_352MB 0x0B + #define IGD_MEMSIZE_384MB 0x0C + #define IGD_MEMSIZE_416MB 0x0D + #define IGD_MEMSIZE_448MB 0x0E + #define IGD_MEMSIZE_480MB 0x0F + #define IGD_MEMSIZE_512MB 0x10 + #define IGD_MEMSIZE_MULTIPLIER 32 + + /* + * Selection 0x1 , "128 MB" + * Selection 0x2 , "256 MB" + * Selection 0x3 , "512 MB" + */ + uint8_t ApertureSize; + #define APERTURE_SIZE_DEFAULT 0 + #define APERTURE_SIZE_128MB 1 + #define APERTURE_SIZE_256MB 2 + #define APERTURE_SIZE_512MB 3 + #define APERTURE_SIZE_BASE 64 + + /* + * Selection 0x1 , "1 MB" + * Selection 0x2 , "2 MB" + */ + uint8_t GttSize; + #define GTT_SIZE_DEFAULT 0 + #define GTT_SIZE_1MB 1 + #define GTT_SIZE_2MB 2 + + /* + * Enable PCI Mode for LPSS SIO devices. + * If disabled, LPSS SIO devices will run in ACPI mode. + */ + uint8_t LpssSioEnablePciMode; + #define LPSS_PCI_MODE_DEFAULT 0x00 + #define LPSS_PCI_MODE_DISABLE 0x01 + #define LPSS_PCI_MODE_ENABLE 0x02 + + /* modifiers for various enables */ + uint8_t AzaliaAutoEnable; + #define AZALIA_FOLLOWS_DEVICETREE 0 + #define AZALIA_FSP_AUTO_ENABLE 1 + + uint8_t LpeAcpiModeEnable; + #define LPE_ACPI_MODE_DISABLED 1 + #define LPE_ACPI_MODE_ENABLED 2 + +/* ***** ACPI configuration ***** */ + /* Options for these are in src/arch/x86/include/arch/acpi.h */ + uint8_t fadt_pm_profile; + uint16_t fadt_boot_arch; + +}; + +extern struct chip_operations soc_intel_fsp_baytrail_ops; +#endif /* _FSP_BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c new file mode 100644 index 0000000..f260880 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <reg_script.h> + +#include <baytrail/msr.h> +#include <baytrail/pattrs.h> +#include <baytrail/ramstage.h> +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#include <baytrail/smm.h> + +static void smm_relocate(void *unused); +static void enable_smis(void *unused); + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + /* Wait for APs to finish initialization before proceeding. */ + MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), +}; +#else /* CONFIG_HAVE_SMI_HANDLER */ +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), +}; +#endif + +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} + +/* Core level MSRs */ +const struct reg_script core_msr_script[] = { + /* Dynamic L2 shrink enable and threshold */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_MSR_OR(MSR_POWER_MISC, 0x44), + REG_SCRIPT_END +}; + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + const struct pattrs *pattrs = pattrs_get(); + struct mp_params mp_params; + + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + mp_params.num_cpus = pattrs->num_cpus, + mp_params.parallel_microcode_load = 0, + mp_params.adjust_apic_id = adjust_apic_id; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = 0; + + if (mp_init(cpu_bus, &mp_params)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } +} + +static void baytrail_core_init(device_t cpu) +{ + printk(BIOS_DEBUG, "Init BayTrail core.\n"); + + /* On bay trail the turbo disable bit is actually scoped at building + * block level -- not package. For non-bsp cores that are within a + * building block enable turbo. The cores within the BSP's building + * block will just see it already enabled and move on. */ + if (lapicid()) + enable_turbo(); + + /* Set core MSRs */ + reg_script_run(core_msr_script); + + /* Set this core to max frequency ratio */ + set_max_freq(); +} + +static struct device_operations cpu_dev_ops = { + .init = baytrail_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x30671 }, + { X86_VENDOR_INTEL, 0x30672 }, + { X86_VENDOR_INTEL, 0x30673 }, + { X86_VENDOR_INTEL, 0x30678 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +/* + * SMM loading and initialization. + */ + +struct smm_relocation_attrs { + uint32_t smbase; + uint32_t smrr_base; + uint32_t smrr_mask; +}; + +static struct smm_relocation_attrs relo_attrs; + +static void adjust_apic_id_map(struct smm_loader_params *smm_params) +{ + int i; + struct smm_runtime *runtime = smm_params->runtime; + + for (i = 0; i < CONFIG_MAX_CPUS; i++) + runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); +} + +static void asmlinkage +cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime) +{ +#ifndef CONFIG_MAX_CPUS +#error CONFIG_MAX_CPUS must be set. +#endif + msr_t smrr; + em64t100_smm_state_save_area_t *smm_state; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + /* Set up SMRR. */ + smrr.lo = relo_attrs.smrr_base; + smrr.hi = 0; + wrmsr(SMRRphysBase_MSR, smrr); + smrr.lo = relo_attrs.smrr_mask; + smrr.hi = 0; + wrmsr(SMRRphysMask_MSR, smrr); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); + smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; + printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); +} + +static int install_relocation_handler(int num_cpus) +{ + const int save_state_size = sizeof(em64t100_smm_state_save_area_t); + + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = (smm_handler_t)&cpu_smm_do_relocation, + }; + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static int install_permanent_handler(int num_cpus) +{ +#ifndef CONFIG_SMM_RESERVED_SIZE +#error CONFIG_SMM_RESERVED_SIZE must be set. +#endif + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t100_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_attrs.smbase); + + if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static int smm_load_handlers(void) +{ + /* All range registers are aligned to 4KiB */ + const uint32_t rmask = ~((1 << 12) - 1); + const struct pattrs *pattrs = pattrs_get(); + + /* Initialize global tracking state. */ + relo_attrs.smbase = (uint32_t)smm_region_start(); + relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; + relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; + relo_attrs.smrr_mask |= MTRRphysMaskValid; + + /* Install handlers. */ + if (install_relocation_handler(pattrs->num_cpus) < 0) { + printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); + return -1; + } + + if (install_permanent_handler(pattrs->num_cpus) < 0) { + printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + + return 0; +} + +static void smm_relocate(void *unused) +{ + + /* Load relocation and permanent handler. */ + if (boot_cpu()) { + if (smm_load_handlers() < 0) { + printk(BIOS_ERR, "Error loading SMM handlers.\n"); + return; + } + southcluster_smm_clear_state(); + } + + /* Relocate SMM space. */ + smm_initiate_relocation(); +} + +static void enable_smis(void *unused) +{ + southcluster_smm_enable_smi(); +} +#endif diff --git a/src/soc/intel/fsp_baytrail/ehci.c b/src/soc/intel/fsp_baytrail/ehci.c new file mode 100644 index 0000000..b9a3f9e --- /dev/null +++ b/src/soc/intel/fsp_baytrail/ehci.c @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/ramstage.h> +#include <baytrail/ehci.h> + +#include "chip.h" + +static const struct reg_script ehci_init_script[] = { + /* Enable S0 PLL shutdown + * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ + REG_PCI_OR16(0x7a, 0x14de), + /* Enable SB local clock gating + * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */ + REG_PCI_OR32(0x7c, 0x0000000c), + REG_PCI_OR32(0x8c, 0x00000001), + /* Enable dynamic clock gating 0x4001=0xCE */ + REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE), + /* Magic RCBA register set sequence */ + /* RCBA + 0x200=0x1 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001), + /* RCBA + 0x204=0x2 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002), + /* RCBA + 0x208=0x0 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000), + /* RCBA + 0x240[4,3,2,1,0]=00000b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0), + /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007), + /* RCBA + 0x31c[3,2,1,0]=0011b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_clock_gating_script[] = { + /* Enable SB local clock gating */ + REG_PCI_OR32(0x7c, 0x00004000), + /* RCBA + 0x284=0xbe (step B0+) */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_disable_script[] = { + /* Clear Run/Stop Bit */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), + /* Wait for HC Halted */ + REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, + USB2STS_HCHALT, USB2STS_HCHALT, 10000), + /* Disable Interrupts */ + REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), + /* Disable Asynchronous and Periodic Scheduler */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, + ~(USB2CMD_ASE | USB2CMD_PSE), 0), + /* Disable port wake */ + REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), + /* Set Function Disable bit in RCBA */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_hc_reset[] = { + REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), + REG_SCRIPT_END +}; + +static void usb2_phy_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + struct reg_script usb2_phy_script[] = { + /* USB3PHYInit() */ + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700), + /* Per port phy settings, set in devicetree.cb */ + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, + config->usb2_per_port_lane0), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP0, + config->usb2_per_port_rcomp_hs_pullup0), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, + config->usb2_per_port_lane1), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP1, + config->usb2_per_port_rcomp_hs_pullup1), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, + config->usb2_per_port_lane2), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP2, + config->usb2_per_port_rcomp_hs_pullup2), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, + config->usb2_per_port_lane3), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP3, + config->usb2_per_port_rcomp_hs_pullup3), + REG_SCRIPT_END + }; + + if (config->usb2_per_port_lane0) + reg_script_run(usb2_phy_script); +} + +static void ehci_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + struct reg_script ehci_hc_init[] = { + /* Controller init */ + REG_SCRIPT_NEXT(ehci_init_script), + /* Enable clock gating */ + REG_SCRIPT_NEXT(ehci_clock_gating_script), + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), + REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), + /* Close per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), + REG_SCRIPT_END + }; + + /* Don't reset controller in S3 resume path */ + if (acpi_slp_type != 3) + reg_script_run_on_dev(dev, ehci_hc_reset); + + /* Disable controller if ports are routed to XHCI */ + if (config->usb_route_to_xhci) { + /* Disable controller */ + reg_script_run_on_dev(dev, ehci_disable_script); + + /* Hide device with southcluster function */ + dev->enabled = 0; + southcluster_enable_dev(dev); + } else { + /* Initialize EHCI controller */ + reg_script_run_on_dev(dev, ehci_hc_init); + } + + /* Setup USB2 PHY based on board config */ + usb2_phy_init(dev); +} + +static struct device_operations ehci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ehci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_ehci __pci_driver = { + .ops = &ehci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = EHCI_DEVID +}; diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig new file mode 100644 index 0000000..5df6374 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BAYTRAIL_FSP_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP + select USE_GENERIC_FSP_CAR_INC + select FSP_USES_UPD + +config FSP_FILE + string + default "../intel/fsp/baytrail/FvFsp.bin" + help + The path and filename of the Intel FSP binary for this platform. + diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc new file mode 100644 index 0000000..ebdc80a --- /dev/null +++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chipset_fsp_util.c +romstage-y += chipset_fsp_util.c + diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c new file mode 100644 index 0000000..f847e21 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -0,0 +1,325 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cpu/x86/stack.h> +#include <console/console.h> +#include <bootstate.h> +#include <cbmem.h> +#include <device/device.h> +#include <baytrail/pci_devs.h> +#include <drivers/intel/fsp/fsp_util.h> +#include "../chip.h" +#include <baytrail/reset.h> + +#ifdef __PRE_RAM__ +#include <baytrail/romstage.h> +#endif + +#ifdef __PRE_RAM__ + +/* Copy the default UPD region and settings to a buffer for modification */ +static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) +{ + VPD_DATA_REGION *VpdDataRgnPtr; + UPD_DATA_REGION *UpdDataRgnPtr; + VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); + UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); + memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); +} + +/* default to just enabling HDMI audio */ +const PCH_AZALIA_CONFIG mAzaliaConfig = { + .Pme = 1, + .DS = 1, + .DA = 0, + .HdmiCodec = 1, + .AzaliaVCi = 1, + .Rsvdbits = 0, + .AzaliaVerbTableNum = 0, + .AzaliaVerbTable = NULL, + .ResetWaitTimer = 300 +}; + +typedef struct soc_intel_fsp_baytrail_config config_t; + +/** + * Update the UPD data based on values from devicetree.cb + * + * @param UpdData Pointer to the UPD Data structure + */ +static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) +{ + ROMSTAGE_CONST struct device *dev; + ROMSTAGE_CONST config_t *config; + printk(BIOS_DEBUG, "Configure Default UPD Data\n"); + + dev = dev_find_slot(0, SOC_DEV_FUNC); + config = dev->chip_info; + + /* Set up default verb tables - Just HDMI audio */ + UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; + + /* Set SPD addresses */ + if (config->MrcInitSPDAddr1 == SPD_ADDR_DISABLED) + UpdData->PcdMrcInitSPDAddr1 = 0x00; + else if (config->MrcInitSPDAddr1 != SPD_ADDR_DEFAULT) + UpdData->PcdMrcInitSPDAddr1 = config->MrcInitSPDAddr1; + printk(BIOS_DEBUG, "SPD Addr1:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr1); + + if (config->MrcInitSPDAddr2 == SPD_ADDR_DISABLED) + UpdData->PcdMrcInitSPDAddr2 = 0x00; + else if (config->MrcInitSPDAddr2 != SPD_ADDR_DEFAULT) + UpdData->PcdMrcInitSPDAddr2 = config->MrcInitSPDAddr2; + printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2); + + if (config->SataMode != SATA_MODE_DEFAULT) + UpdData->PcdSataMode = config->SataMode - SATA_MODE_IDE; + + if ((config->eMMCBootMode != EMMC_USE_DEFAULT) || + (config->eMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) + UpdData->PcdeMMCBootMode = config->eMMCBootMode; + + if (config->LpssSioEnablePciMode != LPSS_PCI_MODE_DEFAULT) + UpdData->PcdLpssSioEnablePciMode = config->LpssSioEnablePciMode - + LPSS_PCI_MODE_DISABLE; + + if (config->MrcInitTsegSize != TSEG_SIZE_DEFAULT) + UpdData->PcdMrcInitTsegSize = config->MrcInitTsegSize; + printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); + + if (config->MrcInitMmioSize != MMIO_SIZE_DEFAULT) + UpdData->PcdMrcInitMmioSize = config->MrcInitMmioSize; + printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); + + if (config->IgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT) + UpdData->PcdIgdDvmt50PreAlloc = config->IgdDvmt50PreAlloc; + printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n", + UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); + + if (config->ApertureSize != APERTURE_SIZE_DEFAULT) + UpdData->PcdApertureSize = config->ApertureSize; + printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n", + APERTURE_SIZE_BASE << UpdData->PcdApertureSize); + + if (config->GttSize != GTT_SIZE_DEFAULT) + UpdData->PcdGttSize = config->GttSize; + printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); + + /* + * Loop through all the SOC devices in the devicetree + * enabling and disabling the them as requested. + */ + for (; dev; dev = dev_find_next_pci_device(dev)) { + + config = dev->chip_info; + + switch (dev->path.pci.devfn) { + case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + UpdData->ISPEnable = dev->enabled; + printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n", + UpdData->PcdEnableSdio?"Enabled":"Disabled"); + break; + case EMMC_DEV_FUNC: /* EMMC 4.1*/ + if ((dev->enabled) && + (config->eMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) + UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; + break; + case SDIO_DEV_FUNC: + UpdData->PcdEnableSdio = dev->enabled; + printk(BIOS_DEBUG, "Sdio:\t\t\t%s\n", + UpdData->PcdEnableSdio?"Enabled":"Disabled"); + break; + case SD_DEV_FUNC: + UpdData->PcdEnableSdcard = dev->enabled; + printk(BIOS_DEBUG, "Sdcard:\t\t\t%s\n", + UpdData->PcdEnableSdcard?"Enabled":"Disabled"); + break; + case SATA_DEV_FUNC: + UpdData->PcdEnableSata = dev->enabled; + printk(BIOS_DEBUG, "Sata:\t\t\t%s\n", + UpdData->PcdEnableSata?"Enabled":"Disabled"); + if (UpdData->PcdEnableSata) + printk(BIOS_DEBUG, "SATA Mode:\t\t%s\n", + UpdData->PcdSataMode?"AHCI":"IDE"); + break; + case XHCI_DEV_FUNC: + UpdData->PcdEnableXhci = dev->enabled; + break; + case LPE_DEV_FUNC: + if (dev->enabled && config->LpeAcpiModeEnable == + LPE_ACPI_MODE_ENABLED) + UpdData->PcdEnableLpe = LPE_ACPI_MODE_ENABLED; + else + UpdData->PcdEnableLpe = dev->enabled; + printk(BIOS_DEBUG, "Lpe:\t\t\t%s\n", + UpdData->PcdEnableLpe?"Enabled":"Disabled"); + printk(BIOS_DEBUG, "Lpe mode:\t\t%s\n", + UpdData->PcdEnableLpe == LPE_ACPI_MODE_ENABLED? + "ACPI":"PCI"); + break; + case MMC45_DEV_FUNC: /* MMC 4.5*/ + if ((dev->enabled) && + (config->eMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) + UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; + break; + case SIO_DMA1_DEV_FUNC: + UpdData->PcdEnableDma0 = dev->enabled; + printk(BIOS_DEBUG, "SIO Dma 0:\t\t%s\n", + UpdData->PcdEnableDma0?"Enabled":"Disabled"); + break; + case I2C1_DEV_FUNC: + UpdData->PcdEnableI2C0 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C0:\t\t%s\n", + UpdData->PcdEnableI2C0?"Enabled":"Disabled"); + break; + case I2C2_DEV_FUNC: + UpdData->PcdEnableI2C1 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C1:\t\t%s\n", + UpdData->PcdEnableI2C1?"Enabled":"Disabled"); + break; + case I2C3_DEV_FUNC: + UpdData->PcdEnableI2C2 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C2:\t\t%s\n", + UpdData->PcdEnableI2C2?"Enabled":"Disabled"); + break; + case I2C4_DEV_FUNC: + UpdData->PcdEnableI2C3 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C3:\t\t%s\n", + UpdData->PcdEnableI2C3?"Enabled":"Disabled"); + break; + case I2C5_DEV_FUNC: + UpdData->PcdEnableI2C4 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C4:\t\t%s\n", + UpdData->PcdEnableI2C4?"Enabled":"Disabled"); + break; + case I2C6_DEV_FUNC: + UpdData->PcdEnableI2C5 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C5:\t\t%s\n", + UpdData->PcdEnableI2C5?"Enabled":"Disabled"); + break; + case I2C7_DEV_FUNC: + UpdData->PcdEnableI2C6 = dev->enabled; + printk(BIOS_DEBUG, "SIO I2C6:\t\t%s\n", + UpdData->PcdEnableI2C6?"Enabled":"Disabled"); + break; + case TXE_DEV_FUNC: /* TXE */ + break; + case HDA_DEV_FUNC: + if (config->AzaliaAutoEnable) { + UpdData->PcdEnableAzalia = 2; + printk(BIOS_DEBUG, "Azalia:\t\t\tAuto\n"); + } else { + UpdData->PcdEnableAzalia = dev->enabled; + printk(BIOS_DEBUG, "Azalia:\t\t\t%s\n", + UpdData->PcdEnableAzalia?"Enabled":"Disabled"); + } + break; + case PCIE_PORT1_DEV_FUNC: + case PCIE_PORT2_DEV_FUNC: + case PCIE_PORT3_DEV_FUNC: + case PCIE_PORT4_DEV_FUNC: + break; + case EHCI_DEV_FUNC: + UpdData->PcdEnableXhci = !(dev->enabled); + break; + case SIO_DMA2_DEV_FUNC: + UpdData->PcdEnableDma1 = dev->enabled; + printk(BIOS_DEBUG, "SIO Dma1:\t\t%s\n", + UpdData->PcdEnableDma1?"Enabled":"Disabled"); + break; + case PWM1_DEV_FUNC: + UpdData->PcdEnablePwm0 = dev->enabled; + printk(BIOS_DEBUG, "Pwm0\t\t\t%s\n", + UpdData->PcdEnablePwm0?"Enabled":"Disabled"); + break; + case PWM2_DEV_FUNC: + UpdData->PcdEnablePwm1 = dev->enabled; + printk(BIOS_DEBUG, "Pwm1:\t\t\t%s\n", + UpdData->PcdEnablePwm1?"Enabled":"Disabled"); + break; + case HSUART1_DEV_FUNC: + UpdData->PcdEnableHsuart0 = dev->enabled; + printk(BIOS_DEBUG, "Hsuart0:\t\t%s\n", + UpdData->PcdEnableHsuart0?"Enabled":"Disabled"); + break; + case HSUART2_DEV_FUNC: + UpdData->PcdEnableHsuart1 = dev->enabled; + printk(BIOS_DEBUG, "Hsuart1:\t\t%s\n", + UpdData->PcdEnableHsuart1?"Enabled":"Disabled"); + break; + case SPI_DEV_FUNC: + UpdData->PcdEnableSpi = dev->enabled; + printk(BIOS_DEBUG, "Spi:\t\t\t%s\n", + UpdData->PcdEnableSpi?"Enabled":"Disabled"); + break; + case LPC_DEV_FUNC: /* LPC */ + break; + case SMBUS_DEV_FUNC: + break; + } + } + + if(UpdData->PcdeMMCBootMode == EMMC_AUTO - EMMC_DISABLED) { + printk(BIOS_DEBUG, "eMMC Mode:\t\tAuto"); + } else { + printk(BIOS_DEBUG, "eMMC 4.1:\t\t%s\n", + UpdData->PcdeMMCBootMode == EMMC_4_1 - EMMC_DISABLED? + "Enabled":"Disabled"); + printk(BIOS_DEBUG, "eMMC 4.5:\t\t%s\n", + UpdData->PcdeMMCBootMode == EMMC_4_5 - EMMC_DISABLED? + "Enabled":"Disabled"); + } + printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + +} + +/* Set up the Baytrail specific structures for the call into the FSP */ +void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, + FSP_INFO_HEADER *fsp_ptr) +{ + FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; + + /* Initialize the UPD Data */ + GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); + ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); + pFspInitParams->NvsBufferPtr = NULL; + pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; + +#if IS_ENABLED(CONFIG_ENABLE_FAST_BOOT) + /* Find the fastboot cache that was saved in the ROM */ + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); +#endif + + return; +} + +/* The FSP returns here after the fsp_early_init call */ +void ChipsetFspReturnPoint(EFI_STATUS Status, + VOID *HobListPtr) +{ + if (Status == 0xFFFFFFFF) { + warm_reset(); + } + romstage_main_continue(Status, HobListPtr); +} + +#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h new file mode 100644 index 0000000..1b60398 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CHIPSET_FSP_UTIL_H +#define CHIPSET_FSP_UTIL_H + +#include <fsp.h> +#include <fsptypes.h> +#include <fspfv.h> +#include <fspffs.h> +#include <fspapi.h> +#include <fspplatform.h> +#include <fspinfoheader.h> +#include <fsphob.h> +#include <fspvpd.h> +#include <azalia.h> + +#define FSP_RESERVE_MEMORY_SIZE 0x200000 + +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +/* + * The FSP Image ID is different for each platform's FSP and + * can be used to verify that the right FSP binary is loaded. + * For the Bay Trail FSP, the Image Id is "VLYVIEW0". + */ +#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ +#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ + +#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c new file mode 100644 index 0000000..8cde60d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <console/console.h> +#include <baytrail/gpio.h> +#include <baytrail/pmc.h> + +/* GPIO-to-Pad LUTs */ +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = + { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ + 2, 5, 9 }; /* [24:26] */ + +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = + { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ + 106, 87, 91, 104, 97, 100 }; /* [96:101] */ + +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = + { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ + 52, 53, 59, 40 }; /* [40:43] */ + +/* GPIO bank descriptions */ +static const struct gpio_bank gpncore_bank = { + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpscore_bank = { + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpssus_bank = { + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, + .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, +}; + +static void setup_gpios(const struct soc_gpio_map *gpios, + const struct gpio_bank *bank) +{ + const struct soc_gpio_map *config; + int gpio = 0; + u32 reg, pad_conf0; + u8 set, bit; + + u32 use_sel[4] = {0}; + u32 io_sel[4] = {0}; + u32 gp_lvl[4] = {0}; + u32 tpe[4] = {0}; + u32 tne[4] = {0}; + u32 wake_en[4] = {0}; + + if (!gpios) + return; + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; + config++, gpio++) { + if (gpio > bank->gpio_count) + break; + + set = gpio >> 5; + bit = gpio % 32; + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) { + /* Legacy IO configuration */ + use_sel[set] |= config->use_sel << bit; + io_sel[set] |= config->io_sel << bit; + gp_lvl[set] |= config->gp_lvl << bit; + tpe[set] |= config->tpe << bit; + tne[set] |= config->tne << bit; + + /* Some banks do not have wake_en ability */ + if (bank->has_wake_en) + wake_en[set] |= config->wake_en << bit; + } + + /* Pad configuration registers */ + reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; + + /* Add correct func to GPIO pad config */ + pad_conf0 = config->pad_conf0; + if (config->is_gpio) + { + if (gpio >= bank->gpio_f1_range_start && + gpio <= bank->gpio_f1_range_end) + pad_conf0 |= PAD_FUNC1; + else + pad_conf0 |= PAD_FUNC0; + } + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", + reg, pad_conf0, config->pad_conf1, config->pad_val); +#endif + + write32(reg + PAD_CONF0_REG, pad_conf0); + write32(reg + PAD_CONF1_REG, config->pad_conf1); + write32(reg + PAD_VAL_REG, config->pad_val); + } + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) + for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { + reg = bank->legacy_base + 0x20 * set; + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, + "Write GPIO: Reg(%x) - %x %x %x %x %x\n", + reg, use_sel[set], io_sel[set], gp_lvl[set], + tpe[set], tne[set]); +#endif + + outl(use_sel[set], reg + LEGACY_USE_SEL_REG); + outl(io_sel[set], reg + LEGACY_IO_SEL_REG); + outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); + outl(tpe[set], reg + LEGACY_TPE_REG); + outl(tne[set], reg + LEGACY_TNE_REG); + + /* TS registers are WOC */ + outl(0, reg + LEGACY_TS_REG); + + if (bank->has_wake_en) + outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); + } +} + +static void setup_gpio_route(const struct soc_gpio_map *sus, + const struct soc_gpio_map *core) +{ + uint32_t route_reg = 0; + int i; + + for (i = 0; i < 8; i++) { + /* SMI takes precedence and wake_en implies SCI. */ + if (sus[i].smi) { + route_reg |= ROUTE_SMI << (2 * i); + } else if (sus[i].sci) { + route_reg |= ROUTE_SCI << (2 * i); + } + + if (core[i].smi) { + route_reg |= ROUTE_SMI << (2 * (i + 8)); + } else if (core[i].sci) { + route_reg |= ROUTE_SCI << (2 * (i + 8)); + } + } +// southcluster_smm_save_gpio_route(route_reg); +} + +static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], + const struct gpio_bank *bank) +{ + u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 val; + int i; + + /* Write all four DIRQ registers */ + for (i=0; i<4; ++i) { + val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | + dirq[i * 4 + 1] << 8 | dirq[i * 4]; + write32(reg + i * 4, val); +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", + reg + i * 4, val); +#endif + } +} + +void setup_soc_gpios(struct soc_gpio_config *config) +{ + if (config) { + setup_gpios(config->ncore, &gpncore_bank); + setup_gpios(config->score, &gpscore_bank); + setup_gpios(config->ssus, &gpssus_bank); + setup_gpio_route(config->ssus, config->score); + + if (config->core_dirq) + setup_dirqs(*config->core_dirq, &gpscore_bank); + if (config->sus_dirq) + setup_dirqs(*config->sus_dirq, &gpssus_bank); + } + +} + +struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +{ + printk(BIOS_DEBUG, "Default/empty GPIO config\n"); + return NULL; +} diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c new file mode 100644 index 0000000..f892b20 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/iosf.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/iosf.h> + +#if !defined(__PRE_RAM__) +#ifndef CONFIG_MMCONF_BASE_ADDRESS +#error CONFIG_MMCONF_BASE_ADDRESS must be set. +#endif +#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) + +static inline void write_iosf_reg(int reg, uint32_t value) +{ + write32(IOSF_PCI_BASE + reg, value); +} +static inline uint32_t read_iosf_reg(int reg) +{ + return read32(IOSF_PCI_BASE + reg); +} +#else +static inline void write_iosf_reg(int reg, uint32_t value) +{ + pci_write_config32(IOSF_PCI_DEV, reg, value); +} +static inline uint32_t read_iosf_reg(int reg) +{ + return pci_read_config32(IOSF_PCI_DEV, reg); +} +#endif + +/* Common sequences for all the port accesses. */ +static uint32_t iosf_read_port(uint32_t cr, int reg) +{ + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +{ + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} + +#define IOSF_READ(port) \ + IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) +#define IOSF_WRITE(port) \ + IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + +uint32_t iosf_bunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(BUNIT), reg); +} + +void iosf_bunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(BUNIT), reg, val); +} + +uint32_t iosf_dunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(SYSMEMC), reg); +} + +uint32_t iosf_dunit_ch0_read(int reg) +{ + return iosf_dunit_read(reg); +} + +uint32_t iosf_dunit_ch1_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + IOSF_PORT(IOSF_PORT_DUNIT_CH1); + return iosf_read_port(cr, reg); +} + +void iosf_dunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); +} + +uint32_t iosf_lpss_read(int reg) +{ + return iosf_read_port(IOSF_READ(LPSS), reg); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(LPSS), reg, val); +} diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c new file mode 100644 index 0000000..2c85ce6 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/lpss.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/iosf.h> +#include <baytrail/nvs.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <baytrail/device_nvs.h> + +#include "chip.h" + +static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +{ + struct reg_script ops[] = { + REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), + REG_SCRIPT_END, + }; + + reg_script_run_on_dev(dev, ops); +} + +static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ + + switch (dev->path.pci.devfn) { + SET_IOSF_REG(SIO_DMA1); + break; + SET_IOSF_REG(I2C1); + break; + SET_IOSF_REG(I2C2); + break; + SET_IOSF_REG(I2C3); + break; + SET_IOSF_REG(I2C4); + break; + SET_IOSF_REG(I2C5); + break; + SET_IOSF_REG(I2C6); + break; + SET_IOSF_REG(I2C7); + break; + SET_IOSF_REG(SIO_DMA2); + break; + SET_IOSF_REG(PWM1); + break; + SET_IOSF_REG(PWM2); + break; + SET_IOSF_REG(HSUART1); + break; + SET_IOSF_REG(HSUART2); + break; + SET_IOSF_REG(SPI); + break; + } +} + +static void i2c_disable_resets(device_t dev) +{ + /* Release the I2C devices from reset. */ + static const struct reg_script ops[] = { + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_SCRIPT_END, + }; + +#define CASE_I2C(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1): + CASE_I2C(I2C2): + CASE_I2C(I2C3): + CASE_I2C(I2C4): + CASE_I2C(I2C5): + CASE_I2C(I2C6): + CASE_I2C(I2C7): + printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); + reg_script_run_on_dev(dev, ops); + break; + default: + return; + } +} + +static void lpss_init(device_t dev) +{ + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", + slot, func); + return; + } + dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpss_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + SIO_DMA1_DEVID, + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + SIO_DMA2_DEVID, + PWM1_DEVID, + PWM2_DEVID, + HSUART1_DEVID, + HSUART2_DEVID, + SPI_DEVID, + 0, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c new file mode 100644 index 0000000..83858b8 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <baytrail/iosf.h> +#include <baytrail/smm.h> + +void *smm_region_start(void) +{ + return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); +} diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc new file mode 100644 index 0000000..012c712 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + +ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) +ifneq ($(wildcard $(shell realpath -q -L "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) +CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) +endif +endif diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c new file mode 100644 index 0000000..9df84dd --- /dev/null +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { + +/* Size is 0xCC00 - update in Kconfig when the patch gets updated. */ +#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 + +}; diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c new file mode 100644 index 0000000..c09ae4c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/lapic.h> +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <device/pci.h> +#include <cbmem.h> +#include <baytrail/baytrail.h> +#include <drivers/intel/fsp/fsp_util.h> + + +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +/* Host Memory Map: + * + * +--------------------------+ BMBOUND_HI + * | Usable DRAM | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ BMBOUND + * | TPM | + * +--------------------------+ IMR2 + * | TXE | + * +--------------------------+ IMR1 + * | iGD | + * +--------------------------+ + * | GTT | + * +--------------------------+ SMMRRH, IRM0 + * | TSEG | + * +--------------------------+ SMMRRL + * | FSP | + * +--------------------------+ SMMRRL - 2MB + * | Usable DRAM | + * +--------------------------+ FFFFF + * | ROM Area | + * +--------------------------+ A0000 + * | Usable DRAM | + * +--------------------------+ 0 + * + * Note that there are really only a few regions that need to enumerated w.r.t. + * coreboot's resource model: + * + * +--------------------------+ BMBOUND_HI + * | Cacheable/Usable | + * +--------------------------+ 4GiB + * + * +--------------------------+ BMBOUND + * | Uncacheable/Reserved | + * +--------------------------+ SMMRRH + * | Cacheable/Reserved | + * +--------------------------+ SMMRRL + * | Cacheable/Usable | + * +--------------------------+ 0 + */ + +/* + * Get the top of low memory for use by ACPI + */ +uint32_t nc_read_top_of_low_memory(void) +{ + uint32_t fsp_mem_base = 0; + GetLowMemorySize(&fsp_mem_base); + + return fsp_mem_base; +} + +static int get_pcie_bar(u32 *base, u32 *len) +{ + device_t dev; + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return 0; + + pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + *len = 256 * 1024 * 1024; /* 256MB ECAM range */ + return 1; + +} + +static int add_fixed_resources(struct device *dev, int index) +{ + struct resource *resource; + u32 pcie_config_base, pcie_config_size; + + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + resource = new_resource(dev, index++); + resource->base = (resource_t) pcie_config_base; + resource->size = (resource_t) pcie_config_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + resource = new_resource(dev, index++); /* Local APIC */ + resource->base = LAPIC_DEFAULT_BASE; + resource->size = 0x00001000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + + return index; +} + +static void mc_add_dram_resources(device_t dev) +{ + u32 bmbound, bsmmrrl; + int index = 0; + uint64_t highmem_size = 0; + uint32_t fsp_mem_base = 0; + + GetHighMemorySize(&highmem_size); + GetLowMemorySize(&fsp_mem_base); + + + bmbound = iosf_bunit_read(BUNIT_BMBOUND); + bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; + + if (bsmmrrl){ + printk(BIOS_DEBUG, "UMA, GTT & SMM memory location: 0x%x\n" + "UMA, GTT & SMM memory size: %dM\n", + bsmmrrl, (bmbound - bsmmrrl) >> 20); + + printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", + fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); + + if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) + printk(BIOS_WARNING, "Warning: Fsp memory size does not match " + "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); + } + + printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n", + fsp_mem_base, fsp_mem_base >> 20); + + /* Report the memory regions. */ + ram_resource(dev, index++, 0, legacy_hole_base_k); + ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, + ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); + + /* Mark SMM & FSP regions reserved */ + mmio_resource(dev, index++, fsp_mem_base >> 10, + (bmbound - fsp_mem_base) >> 10); + + if (highmem_size) { + ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 ); + } + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", + highmem_size >> 20); + + index = add_fixed_resources(dev, index); +} + +static void nc_read_resources(device_t dev) +{ + /* Call the normal read_resources */ + pci_dev_read_resources(dev); + + + /* For some reason the graphics pci device (0, 2, 0) and the SoC + * transaction router are coming up with the same device id. */ + if (dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)) == dev) { + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev); + } +} + +static void nc_enable(device_t dev) +{ + print_fsp_info(); +} + +static struct device_operations nc_ops = { + .read_resources = nc_read_resources, + .set_resources = NULL, + .enable_resources = NULL, + .init = NULL, + .enable = &nc_enable, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver nc_driver __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SOC_DEVID, +}; + diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c new file mode 100644 index 0000000..dab87ae --- /dev/null +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stddef.h> +#include <console/console.h> +#include <string.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <baytrail/nvm.h> + +/* This module assumes the flash is memory mapped just below 4GiB in the + * address space for reading. Also this module assumes an area it erased + * when all bytes read as all 0xff's. */ + +static struct spi_flash *flash; + +static int nvm_init(void) +{ + if (flash != NULL) + return 0; + + spi_init(); + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return -1; + } + + return 0; +} + +/* Convert memory mapped pointer to flash offset. */ +static inline uint32_t to_flash_offset(void *p) +{ +#ifndef CONFIG_ROM_SIZE +#error CONFIG_ROM_SIZE must be set. +#endif + return CONFIG_ROM_SIZE + (uintptr_t)p; +} + +int nvm_is_erased(const void *start, size_t size) +{ + const uint8_t *cur = start; + const uint8_t erased_value = 0xff; + + while (size > 0) { + if (*cur != erased_value) + return 0; + cur++; + size--; + } + return 1; +} + +int nvm_erase(void *start, size_t size) +{ + if (nvm_init() < 0) + return -1; + flash->erase(flash, to_flash_offset(start), size); + return 0; +} + +/* Write data to NVM. Returns 0 on success < 0 on error. */ +int nvm_write(void *start, const void *data, size_t size) +{ + if (nvm_init() < 0) + return -1; + flash->write(flash, to_flash_offset(start), size, data); + return 0; +} diff --git a/src/soc/intel/fsp_baytrail/placeholders.c b/src/soc/intel/fsp_baytrail/placeholders.c new file mode 100644 index 0000000..c9a9da4 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/placeholders.c @@ -0,0 +1,15 @@ + +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include <device/pci_rom.h> +#include <baytrail/acpi.h> + + +void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +void smm_init(void) {} +#endif + +/* Rmodules don't like weak symbols. */ +u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c new file mode 100644 index 0000000..aee3726 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> + +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> + +#if defined(__SMM__) + +static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); + +static inline device_t get_pcu_dev(void) +{ + return pcu_dev; +} + +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> + +static device_t pcu_dev; +static device_t get_pcu_dev(void) +{ + if (pcu_dev == NULL) + pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); + return pcu_dev; +} +#endif + +uint16_t get_pmbase(void) +{ + return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; +} + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static void print_status_bits(uint32_t status, const char *bit_names[]) +{ + print_num_status_bits(32, status, bit_names); +} + +static uint32_t print_smi_status(uint32_t smi_sts) +{ + static const char *smi_sts_bits[] = { + [2] = "BIOS", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", + [12] = "DEVMON", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "ILB", + [16] = "SMBUS_SMI", + [17] = "LEGACY_USB2", + [18] = "INTEL_USB2", + [20] = "PCI_EXP_SMI", + [26] = "SPI", + [28] = "PUNIT", + [29] = "GUNIT", + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_status_bits(smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +static uint32_t reset_smi_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_sts = inl(pmbase + SMI_STS); + outl(smi_sts, pmbase + SMI_STS); + return smi_sts; +} + +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +void enable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl(pmbase + SMI_EN); + smi_en |= mask; + outl(smi_en, pmbase + SMI_EN); +} + +void disable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl(pmbase + SMI_EN); + smi_en &= ~mask; + outl(smi_en, pmbase + SMI_EN); +} + +void enable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, pmbase + PM1_CNT); +} + +void disable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, pmbase + PM1_CNT); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint16_t pm1_sts = inw(pmbase + PM1_STS); + outw(pm1_sts, pmbase + PM1_STS); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char *pm1_sts_bits[] = { + [0] = "TMROF", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [13] = "USB", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_status_bits(pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +void enable_pm1(uint16_t events) +{ + outw(events, get_pmbase() + PM1_EN); +} + +static uint32_t print_tco_status(uint32_t tco_sts) +{ + static const char *tco_sts_bits[] = { + [3] = "TIMEOUT", + [17] = "SECOND_TO", + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_status_bits(tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +static uint32_t reset_tco_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t tco_sts = inl(pmbase + TCO_STS); + uint32_t tco_en = inl(pmbase + TCO1_CNT); + + outl(tco_sts, pmbase + TCO_STS); + return tco_sts & tco_en; +} + +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +void enable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl(pmbase + GPE0_EN); + gpe0_en |= mask; + outl(gpe0_en, pmbase + GPE0_EN); +} + +void disable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl(pmbase + GPE0_EN); + gpe0_en &= ~mask; + outl(gpe0_en, pmbase + GPE0_EN); +} + +void disable_all_gpe(void) +{ + disable_gpe(~0); +} + + +static uint32_t reset_gpe_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe_sts = inl(pmbase + GPE0_STS); + outl(gpe_sts, pmbase + GPE0_STS); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) +{ + static const char *gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [3] = "PCIE_WAKE0", + [4] = "PUNIT", + [5] = "GUNIT", + [6] = "PCIE_WAKE1", + [7] = "PCIE_WAKE2", + [8] = "PCIE_WAKE3", + [9] = "PCI_EXP", + [10] = "BATLOW", + [13] = "PME_B0", + [16] = "SUS_GPIO_0", + [17] = "SUS_GPIO_1", + [18] = "SUS_GPIO_2", + [19] = "SUS_GPIO_3", + [20] = "SUS_GPIO_4", + [21] = "SUS_GPIO_5", + [22] = "SUS_GPIO_6", + [23] = "SUS_GPIO_7", + [24] = "CORE_GPIO_0", + [25] = "CORE_GPIO_1", + [26] = "CORE_GPIO_2", + [27] = "CORE_GPIO_3", + [28] = "CORE_GPIO_4", + [29] = "CORE_GPIO_5", + [30] = "CORE_GPIO_6", + [31] = "CORE_GPIO_7", + }; + + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_status_bits(gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; +} + +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} + +static uint32_t reset_alt_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); + outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); + return alt_gpio_smi; +} + +static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +{ + uint32_t alt_gpio_sts; + static const char *alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", + [10] = "CORE_GPIO_2", + [11] = "CORE_GPIO_3", + [12] = "CORE_GPIO_4", + [13] = "CORE_GPIO_5", + [14] = "CORE_GPIO_6", + [15] = "CORE_GPIO_7", + }; + + /* Status bits are in the upper 16 bits. */ + alt_gpio_sts = alt_gpio_smi >> 16; + if (!alt_gpio_sts) + return alt_gpio_smi; + + printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); + print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return alt_gpio_smi; +} + +uint32_t clear_alt_status(void) +{ + return print_alt_sts(reset_alt_status()); +} + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32(PMC_BASE_ADDRESS + PRSTS); + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS); + write32(PMC_BASE_ADDRESS + PRSTS, prsts); +} diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c new file mode 100644 index 0000000..f0d13e4 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/raminit.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <cbmem.h> +#include <device/device.h> +#include <baytrail/baytrail.h> +#include <baytrail/iosf.h> +#include <cpu/x86/msr.h> +#include <drivers/intel/fsp/fsp_util.h> + +unsigned long get_top_of_ram(void) +{ + /* + * Get top of usable (low) DRAM. + * FSP puts SMM just below top of low physical (BMBOUND) + */ + u32 tom = iosf_bunit_read(BUNIT_BMBOUND); + u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; + if (bsmmrrl) { + tom = bsmmrrl; + } + tom -= FSP_RESERVE_MEMORY_SIZE; + + return (unsigned long) tom; +} + diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c new file mode 100644 index 0000000..e231701 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdlib.h> + +#include <baytrail/gpio.h> +#include <baytrail/lpc.h> +#include <baytrail/msr.h> +#include <baytrail/pattrs.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + +/* Global PATTRS */ +DEFINE_PATTRS; + +#define SHOW_PATTRS 1 + +static void detect_num_cpus(struct pattrs *attrs) +{ + int ecx = 0; + + while (1) { + struct cpuid_result leaf_b; + + leaf_b = cpuid_ext(0xb, ecx); + + /* Bay Trail doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2). */ + if ((leaf_b.ecx & 0xff00) == 0x0200) { + attrs->num_cpus = leaf_b.ebx & 0xffff; + break; + } + ecx++; + } +} + +static inline void fill_in_msr(msr_t *msr, int idx) +{ + *msr = rdmsr(idx); + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", + idx, msr->hi, msr->lo); + } +} + +static const char *stepping_str[] = { + "A0", "A1", "B0", "B1", "B2", "B3" +}; + +static void fill_in_pattrs(void) +{ + device_t dev; + msr_t msr; + struct pattrs *attrs = (struct pattrs *)pattrs_get(); + + attrs->cpuid = cpuid_eax(1); + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + attrs->revid = pci_read_config8(dev, REVID); + /* The revision to stepping IDs have two values per metal stepping. */ + if (attrs->revid >= RID_B_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; + attrs->stepping += STEP_B0; + } else { + attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; + attrs->stepping += STEP_A0; + } + + attrs->address_bits = cpuid_eax(0x80000008) & 0xff; + detect_num_cpus(attrs); + + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, + "CPUID: %08x\nCores: %d\nRevision ID: %02x\nStepping: %s\n", + attrs->cpuid, attrs->num_cpus, attrs->revid, + (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : + stepping_str[attrs->stepping]); + } + + fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); + + /* Set IA core speed ratio and voltages */ + msr = rdmsr(MSR_IACORE_RATIOS); + attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); + attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + msr = rdmsr(MSR_IACORE_VIDS); + attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_VIDS); + attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + /* Set bus clock speed */ + attrs->bclk_khz = bus_freq_khz(); +} + + +void baytrail_init_pre_device(void) +{ + struct soc_gpio_config *config; + + fill_in_pattrs(); + + /* Allow for SSE instructions to be executed. */ + write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + + /* Get GPIO initial states from mainboard */ + config = mainboard_get_gpios(); + setup_soc_gpios(config); +} diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c new file mode 100644 index 0000000..a421ec9 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/reset.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pmc.h> +#include <baytrail/reset.h> + +void cold_reset(void) +{ + /* S0->S5->S0 trip. */ + outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); +} + +void warm_reset(void) +{ + /* PMC_PLTRST# asserted. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void soft_reset(void) +{ + /* Sends INIT# to CPU */ + outb(RST_CPU, RST_CNT); +} + +void hard_reset(void) +{ + /* Don't power cycle on hard_reset(). It's not really clear what the + * semantics should be for the meaning of hard_reset(). */ + warm_reset(); +} diff --git a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc new file mode 100644 index 0000000..ff7762e --- /dev/null +++ b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Google Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += romstage.c +romstage-y += pmc.c +romstage-y += report_platform.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c + +$(obj)/soc/intel/fsp_baytrail/romstage/romstage.romstage.o : $(obj)/build.h \ No newline at end of file diff --git a/src/soc/intel/fsp_baytrail/romstage/pmc.c b/src/soc/intel/fsp_baytrail/romstage/pmc.c new file mode 100644 index 0000000..678f951 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/romstage/pmc.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/romstage.h> +#include "../chip.h" + +void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c new file mode 100644 index 0000000..37e40ba --- /dev/null +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <baytrail/iosf.h> +#include <baytrail/romstage.h> +#include <cpu/x86/msr.h> +#include <baytrail/msr.h> +#include <cpu/x86/name.h> + +static void print_dram_info(void) +{ + const int mrc_ver_reg = 0xf0; + const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + uint32_t reg; + int num_channels; + int speed; + uint32_t ch0; + uint32_t ch1; + + reg = pci_read_config32(soc_dev, mrc_ver_reg); + + printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); + + /* Number of channels enabled and DDR3 type. Determine number of + * channels by the keying of the rank enable bits [3:0]. * */ + ch0 = iosf_dunit_ch0_read(DRP); + ch1 = iosf_dunit_ch1_read(DRP); + num_channels = 0; + if (ch0 & DRP_RANK_MASK) + num_channels++; + if (ch1 & DRP_RANK_MASK) + num_channels++; + + printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, + (reg & (1 << 22)) ? "LP" : ""); + + /* DRAM frequency -- all channels run at same frequency. */ + reg = iosf_dunit_read(DTR0); + switch (reg & 0x3) { + case 0: + speed = 800; break; + case 1: + speed = 1066; break; + case 2: + speed = 1333; break; + case 3: + speed = 1600; break; + } + printk(BIOS_INFO, "%dMHz\n", speed); +} + +#define VARIANT_ID_BYTE 18 +#define VARIANT_ID_MASK 7 +void report_platform_info(void) +{ + const char *baytrail_variants[4] = { + "Bay Trail-I (ISG/embedded)", + "Bay Trail-T (Tablet)", + "Bay Trail-D (Desktop)", + "Bay Trail-M (Mobile)", + }; + msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID); + uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; + + printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? + baytrail_variants[variant] : "Unknown"); + print_dram_info(); + +} diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c new file mode 100644 index 0000000..2cdb4b5 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -0,0 +1,239 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/cpu.h> +#include <lib.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <romstage_handoff.h> +#include <timestamp.h> +#include <baytrail/gpio.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/romstage.h> +#include <baytrail/acpi.h> +#include <baytrail/baytrail.h> +#include <drivers/intel/fsp/fsp_util.h> +#include <baytrail/pmc.h> +#include <baytrail/spi.h> +#include <build.h> +#include <pc80/mc146818rtc.h> +#include <device/pci_def.h> +#include <console/cbmem_console.h> + +static void program_base_addresses(void) +{ + uint32_t reg; + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, PBASE, reg); + reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, IOBASE, reg); + reg = ILB_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, IBASE, reg); + reg = SPI_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, SBASE, reg); + reg = MPHY_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | RCBA_ENABLE; + pci_write_config32(LPC_BDF, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, ABASE, reg); + reg = GPIO_BASE_ADDRESS | SET_BAR_ENABLE; + pci_write_config32(LPC_BDF, GBASE, reg); +} + +static void spi_init(void) +{ + const uint32_t scs = SPI_BASE_ADDRESS + SCS; + const uint32_t bcr = SPI_BASE_ADDRESS + BCR; + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void baytrail_rtc_init(void) +{ + uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; + uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + int rtc_failed = !!(gen_pmcon1 & RPS); + + if (rtc_failed) { + printk(BIOS_DEBUG, + "RTC Failure detected. Resetting Date to %x/%x/%x%x\n", + COREBOOT_BUILD_MONTH_BCD, + COREBOOT_BUILD_DAY_BCD, + 0x20, + COREBOOT_BUILD_YEAR_BCD); + + write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS); + } + + rtc_init(rtc_failed); +} + +static inline uint32_t *stack_push(u32 *stack, u32 value) +{ + stack = &stack[-1]; + *stack = value; + return stack; +} + +/* Entry from cache-as-ram.inc. */ +void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t fd_mask = 0; + uint32_t fd2_mask = 0; + + post_code(0x40); + + program_base_addresses(); + + post_code(0x41); + tco_disable(); + + post_code(0x42); + byt_config_com1_and_enable(); + + post_code(0x43); + console_init(); + + spi_init(); + baytrail_rtc_init(); + + /* Call into mainboard. */ + early_mainboard_romstage_entry(); + + set_max_freq(); + + post_code(0x44); + + /* Program any required function disables */ + get_func_disables(&fd_mask, &fd2_mask); + + if (fd_mask != 0) { + write32(func_dis, read32(func_dis) | fd_mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (fd2_mask != 0) { + write32(func_dis2, read32(func_dis2) | fd2_mask); + /* Ensure posted write hits. */ + read32(func_dis2); + } + + post_code(0x47); + + /* + * Call early init to initialize memory and chipset. This function returns + * to the romstage_main_continue function with a pointer to the HOB + * structure. + */ + post_code(0x48); + printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); + fsp_early_init(fsp_info_header); + die("Uh Oh! fsp_early_init should not return here.\n"); +} + +/******************************************************************************* + * The FSP early_init function returns to this function. + * Memory is setup and the stack is set by the FSP. + */ +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { + int cbmem_was_initted; + void *cbmem_hob_ptr; + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + tsc_t after_initram_time = rdtsc(); + tsc_t base_time; + base_time.hi = 0; + base_time.lo = 0; +#endif + + post_code(0x4a); + printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", + __func__, (u32) status, (u32) hob_list_ptr); + +#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) + /* FSP reconfigures USB, so reinit it to have debug */ + usbdebug_init(); +#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + + printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); + + report_platform_info(); + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + after_initram_time = rdtsc(); +#endif + post_code(0x4b); + + late_mainboard_romstage_entry(); + post_code(0x4c); + + quick_ram_check(); + post_code(0x4d); + + cbmem_was_initted = !cbmem_recovery(0); + + /* Save the HOB pointer in CBMEM to be used in ramstage*/ + cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; + post_code(0x4e); + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + timestamp_init(base_time); + timestamp_reinit(); + timestamp_add(TS_AFTER_INITRAM, after_initram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) + printk(BIOS_DEBUG, "cbmemc_reinit\n"); + cbmemc_reinit(); +#endif + post_code(0x4f); + + /* Load the ramstage. */ + copy_and_run(); + while (1); +} diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c new file mode 100644 index 0000000..971067f --- /dev/null +++ b/src/soc/intel/fsp_baytrail/romstage/uart.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/gpio.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/romstage.h> + +void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the legacy UART hardware. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} diff --git a/src/soc/intel/fsp_baytrail/sata.c b/src/soc/intel/fsp_baytrail/sata.c new file mode 100644 index 0000000..b1332b0 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/sata.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <baytrail/pci_devs.h> +#include "chip.h" + +typedef struct soc_intel_fsp_baytrail_config config_t; + +static void sata_init(struct device *dev) +{ + u16 reg16; + + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + printk(BIOS_DEBUG, "SATA: Initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); + return; + } + + /* SATA configuration is handled by the FSP */ + + /* Enable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0x0007); + + if (config->SataMode) { + printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); + + /* Initialize AHCI memory-mapped space */ + printk(BIOS_DEBUG, "ABAR: %08X\n", + pci_read_config32(dev, PCI_BASE_ADDRESS_5)); + + } else { + printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); + } + + /* Spin up the drives as early as possible via the Port Enable */ + reg16 = pci_read_config16(dev, SATA_PSC); + reg16 &= ~0x3f; + pci_write_config16(dev, SATA_PSC, reg16); + reg16 = pci_read_config16(dev, SATA_PSC); + reg16 |= 0x3f; + pci_write_config16(dev, SATA_PSC, reg16); + +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + IDE1_DEVID, IDE2_DEVID, /* IDE */ + AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + 0, +}; + +static const struct pci_driver baytrail_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/fsp_baytrail/sd.c b/src/soc/intel/fsp_baytrail/sd.c new file mode 100644 index 0000000..ced2aca --- /dev/null +++ b/src/soc/intel/fsp_baytrail/sd.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/iosf.h> +#include <baytrail/nvs.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include "chip.h" + +#define CAP_OVERRIDE_LOW 0xa0 +#define CAP_OVERRIDE_HIGH 0xa4 +# define USE_CAP_OVERRIDES (1 << 31) + +static void sd_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + + if (config == NULL) + return; + + if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { + printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); + pci_write_config32(dev, CAP_OVERRIDE_LOW, + config->sdcard_cap_low); + pci_write_config32(dev, CAP_OVERRIDE_HIGH, + config->sdcard_cap_high | USE_CAP_OVERRIDES); + } + +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SD_DEVID, +}; diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c new file mode 100644 index 0000000..2225964 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -0,0 +1,406 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <device/pci_def.h> +#include <elog.h> + +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/nvs.h> + +/* GNVS needs to be set by coreboot initiating a software SMI. */ +static global_nvs_t *gnvs; +static int smm_initialized; + +int southbridge_io_trap_handler(int smif) +{ + switch (smif) { + case 0x32: + printk(BIOS_DEBUG, "OS Init\n"); + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ + gnvs->smif = 0; + return 1; /* IO trap handled */ + } + + /* Not handled */ + return 0; +} + +void southbridge_smi_set_eos(void) +{ + enable_smi(EOS); +} + +global_nvs_t *smm_get_gnvs(void) +{ + return gnvs; +} + +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + +static void southbridge_smi_sleep(void) +{ + uint32_t reg32; + uint8_t slp_typ; + uint16_t pmbase = get_pmbase(); + + /* First, disable further SMIs */ + disable_smi(SLP_SMI_EN); + + /* Figure out SLP_TYP */ + reg32 = inl(pmbase + PM1_CNT); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); + slp_typ = (reg32 >> 10) & 7; + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ-2); + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log S3, S4, and S5 entry */ + if (slp_typ >= 5) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); +#endif + + /* Next, do the deed. + */ + + switch (slp_typ) { + case SLP_TYP_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case SLP_TYP_S1: + printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); + break; + case SLP_TYP_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + + /* Invalidate the cache before going to S3 */ + wbinvd(); + break; + case SLP_TYP_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case SLP_TYP_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + + /* Disable all GPE */ + disable_all_gpe(); + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + /* Write back to the SLP register to cause the originally intended + * event again. We need to set BIT13 (SLP_EN) though to make the + * sleep happen. + */ + enable_pm1_control(SLP_EN); + + /* Make sure to stop executing code here for S3/S4/S5 */ + if (slp_typ > 1) + hlt(); + + /* In most sleep states, the code flow of this function ends at + * the line above. However, if we entered sleep state S1 and wake + * up again, we will continue to execute code in this function. + */ + reg32 = inl(pmbase + PM1_CNT); + if (reg32 & SCI_EN) { + /* The OS is not an ACPI OS, so we set the state to S0 */ + disable_pm1_control(SLP_EN | SLP_TYP); + } +} + +/* + * Look for Synchronous IO SMI and use save state from that + * core in case we are not running on the same core that + * initiated the IO transaction. + */ +static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +{ +#ifndef CONFIG_MAX_CPUS +#error CONFIG_MAX_CPUS must be set. +#endif + em64t100_smm_state_save_area_t *state; + int node; + + /* Check all nodes looking for the one that issued the IO */ + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0==1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4==0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return state; + } + + return NULL; +} + +#if IS_ENABLED(CONFIG_ELOG_GSMI) +static void southbridge_smi_gsmi(void) +{ + u32 *ret, *param; + uint8_t sub_command; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); + + if (!io_smi) + return; + + /* Command and return value in EAX */ + ret = (u32*)&io_smi->rax; + sub_command = (uint8_t)(*ret >> 8); + + /* Parameter buffer in EBX */ + param = (u32*)&io_smi->rbx; + + /* drivers/elog/gsmi.c */ + *ret = gsmi_exec(sub_command, param); +} +#endif +static void southbridge_smi_apmc(void) +{ + uint8_t reg8; + em64t100_smm_state_save_area_t *state; + + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(APM_CNT); + switch (reg8) { + case APM_CNT_CST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "C-state control\n"); + break; + case APM_CNT_PST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "P-state control\n"); + break; + case APM_CNT_ACPI_DISABLE: + disable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); + break; + case APM_CNT_ACPI_ENABLE: + enable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); + break; + case APM_CNT_GNVS_UPDATE: + if (smm_initialized) { + printk(BIOS_DEBUG, + "SMI#: SMM structures already initialized!\n"); + return; + } + state = smi_apmc_find_state_save(reg8); + if (state) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)((uint32_t)state->rbx); + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } + break; +#if IS_ENABLED(CONFIG_ELOG_GSMI) + case ELOG_GSMI_APM_CNT: + southbridge_smi_gsmi(); + break; +#endif + } + + mainboard_smi_apmc(reg8); +} + +static void southbridge_smi_pm1(void) +{ + uint16_t pm1_sts = clear_pm1_status(); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed +#if IS_ENABLED(CONFIG_ELOG_GSMI) + elog_add_event(ELOG_TYPE_POWER_BUTTON); +#endif + disable_pm1_control(-1UL); + enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + } +} + +static void southbridge_smi_gpe0(void) +{ + clear_gpe_status(); +} + +static void southbridge_smi_tco(void) +{ + uint32_t tco_sts = clear_tco_status(); + + /* Any TCO event? */ + if (!tco_sts) + return; + + if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ + /* Handle TCO timeout */ + printk(BIOS_DEBUG, "TCO Timeout.\n"); + } +} + +static void southbridge_smi_periodic(void) +{ + uint32_t reg32; + + reg32 = inl(get_pmbase() + SMI_EN); + + /* Are periodic SMIs enabled? */ + if ((reg32 & PERIODIC_EN) == 0) + return; + + printk(BIOS_DEBUG, "Periodic SMI.\n"); +} + +typedef void (*smi_handler_t)(void); + +static const smi_handler_t southbridge_smi[32] = { + NULL, // [0] reserved + NULL, // [1] reserved + NULL, // [2] BIOS_STS + NULL, // [3] LEGACY_USB_STS + southbridge_smi_sleep, // [4] SLP_SMI_STS + southbridge_smi_apmc, // [5] APM_STS + NULL, // [6] SWSMI_TMR_STS + NULL, // [7] reserved + southbridge_smi_pm1, // [8] PM1_STS + southbridge_smi_gpe0, // [9] GPE0_STS + NULL, // [10] reserved + NULL, // [11] reserved + NULL, // [12] reserved + southbridge_smi_tco, // [13] TCO_STS + southbridge_smi_periodic, // [14] PERIODIC_STS + NULL, // [15] SERIRQ_SMI_STS + NULL, // [16] SMBUS_SMI_STS + NULL, // [17] LEGACY_USB2_STS + NULL, // [18] INTEL_USB2_STS + NULL, // [19] reserved + NULL, // [20] PCI_EXP_SMI_STS + NULL, // [21] reserved + NULL, // [22] reserved + NULL, // [23] reserved + NULL, // [24] reserved + NULL, // [25] reserved + NULL, // [26] SPI_STS + NULL, // [27] reserved + NULL, // [28] PUNIT + NULL, // [29] GUNIT + NULL, // [30] reserved + NULL // [31] reserved +}; + +void southbridge_smi_handler(void) +{ + int i; + uint32_t smi_sts; + + /* We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = clear_smi_status(); + + /* Call SMI sub handler for each of the status bits */ + for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { + if (!(smi_sts & (1 << i))) + continue; + + if (southbridge_smi[i] != NULL) { + southbridge_smi[i](); + } else { + printk(BIOS_DEBUG, + "SMI_STS[%d] occured, but no " + "handler available.\n", i); + } + } + + /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. */ + mainboard_smi_gpi(clear_alt_status()); +} diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c new file mode 100644 index 0000000..d4b3d58 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/smm.h> +#include <string.h> + +#include <baytrail/iomap.h> +#include <baytrail/pmc.h> +#include <baytrail/smm.h> + +/* Save the gpio route register. The settings are committed from + * southcluster_smm_enable_smi(). */ +static uint32_t gpio_route; + +void southcluster_smm_save_gpio_route(uint32_t route) +{ + gpio_route = route; +} + +void southcluster_smm_clear_state(void) +{ + uint32_t smi_en; + + /* Log events from chipset before clearing */ + southcluster_log_state(); + + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); + + smi_en = inl(get_pmbase() + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + /* Dump and clear status registers */ + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); + clear_alt_status(); + clear_pmc_status(); +} + +static void southcluster_smm_route_gpios(void) +{ + const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT; + const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; + uint32_t alt_gpio_reg = 0; + uint32_t route_reg = gpio_route; + int i; + + printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); + + /* Start the routing for the specific gpios. */ + write32(gpio_rout, route_reg); + + /* Enable SMIs for the gpios that are set to trigger the SMI. */ + for (i = 0; i < 16; i++) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + alt_gpio_reg |= (1 << i); + } + route_reg >>= 2; + } + printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); + + outl(alt_gpio_reg, alt_gpio_smi); +} + +void southcluster_smm_enable_smi(void) +{ + + printk(BIOS_DEBUG, "Enabling SMIs.\n"); + /* Configure events Disable pcie wake. */ + enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + disable_gpe(PME_B0_EN); + + /* Set up the GPIO route. */ + southcluster_smm_route_gpios(); + + /* Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * No SMIs: + * - on TCO events + * - on microcontroller writes (io 0x62/0x66) + */ + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* + * Issue SMI to set the gnvs pointer in SMM. + * tcg and smi1 are unused. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" ((uint32_t)gnvs), + "d" (APM_CNT) + ); +} diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c new file mode 100644 index 0000000..b7b9186 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -0,0 +1,658 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> +#include <pc80/isa-dma.h> +#include <romstage_handoff.h> + +#include <baytrail/baytrail.h> +#include <baytrail/iomap.h> +#include <baytrail/irq.h> +#include <baytrail/lpc.h> +#include <baytrail/nvs.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/ramstage.h> +#include "chip.h" + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +typedef struct soc_intel_fsp_baytrail_config config_t; + +static inline void +add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +{ + mmio_resource(dev, i, addr >> 10, size >> 10); +} + +static void sc_add_mmio_resources(device_t dev) +{ +#ifndef CONFIG_VIRTUAL_ROM_SIZE +#error CONFIG_VIRTUAL_ROM_SIZE must be set. +#endif + add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); + add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); + add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); + add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); + add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); + add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); + add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); + add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); + add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_VIRTUAL_ROM_SIZE + 1, + CONFIG_VIRTUAL_ROM_SIZE); /* BIOS ROM */ + add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ +} + +/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 + +static void sc_enable_ioapic(struct device *dev) +{ + int i; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f; + + /* + * Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ + write32(ilb_base + ILB_OIC, 0x100); /* AEN */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + /* affirm full set of redirection table entries ("write once") */ + *ioapic_index = 1; + reg32 = *ioapic_data; + *ioapic_index = 1; + *ioapic_data = reg32; + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk(BIOS_SPEW, " reg 0x%04x:", i); + reg32 = *ioapic_data; + printk(BIOS_SPEW, " 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void sc_enable_serial_irqs(struct device *dev) +{ +#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ + /* + * TODO: SERIRQ seems to have a number of problems on baytrail. + * With it enabled, we get some spurious interrupts (ps2) + * in seabios. It also caused IOCHK# NMIs. Remove it + * until we understand how it needs to be configured. + */ + u8 reg8; + u32 ibase = pci_read_config32(dev, IBASE) & ~0xF; + + /* + * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. + */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ + outb(reg8, 0x61); + + write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); + write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); + +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + /* + * SoC requires that the System BIOS first set the SERIRQ logic to + * continuous mode operation for at least one frame before switching + * it into quiet mode operation. + */ + outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ + write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); +#endif +#endif /* DON'T SET UP IRQS */ +} + +/* + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE + * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing + * information to operating systems and drivers. The INT_PIN register is + * generally read only and reports which interrupt pin A - D it uses. The + * INT_LINE register is configurable and reports which IRQ (generally the + * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling + * on devices that are downstream on a PCI bridge into account. + * + * This function will loop through all enabled PCI devices and program the + * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it + * uses. It then configures each interrupt in the pic to be level triggered. + */ +static void write_pci_config_irqs(void) +{ + device_t irq_dev; + device_t targ_dev; + uint8_t int_line = 0; + uint8_t original_int_pin = 0; + uint8_t new_int_pin = 0; + uint16_t current_bdf = 0; + uint16_t parent_bdf = 0; + uint8_t pirq = 0; + uint8_t device_num = 0; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + if (ir == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'global_baytrail_irq_route' structure does not exist\n"); + return; + } + + /* + * Loop through all enabled devices and program their + * INT_LINE, INT_PIN registers from values taken from + * the Interrupt Route registers in the ILB + */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + + if ((irq_dev->path.type != DEVICE_PATH_PCI) || + (!irq_dev->enabled)) + continue; + + current_bdf = irq_dev->path.pci.devfn | + irq_dev->bus->secondary << 8; + + /* + * Step 1: Get the INT_PIN and device structure to look for + * in the pirq_data table defined in the mainboard directory. + */ + targ_dev = NULL; + new_int_pin = get_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + parent_bdf = targ_dev->path.pci.devfn + | targ_dev->bus->secondary << 8; + device_num = PCI_SLOT(parent_bdf); + + if (ir->pcidev[device_num] == 0) { + printk(BIOS_WARNING, + "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", + device_num); + continue; + } + + /* Find the PIRQ that is attached to the INT_PIN this device uses */ + pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; + + /* Get the INT_LINE this device/function will use */ + int_line = ir->pic[pirq]; + + if (int_line != PIRQ_PIC_IRQDISABLE) { + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register in PCI config space */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } else { + /* Set the Interrupt line register as "unknown or unused" */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, + PIRQ_PIC_UNKNOWN_UNUSED); + } + + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", + original_int_pin, pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + new_int_pin, pin_to_str(new_int_pin)); + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); + } + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} + +static void sc_pirq_init(device_t dev) +{ + int i, j; + int pirq; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + /* Set up the PIRQ PIC routing based on static config. */ + printk(BIOS_SPEW, "Start writing IRQ assignments\n" + "PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n" + "IRQ "); + for (i = 0; i < NUM_PIRQS; i++) { + write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); + printk(BIOS_SPEW, "\t%d", ir->pic[i]); + } + printk(BIOS_SPEW, "\n\n"); + + /* Set up the per device PIRQ routing based on static config. */ + printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" + "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); + for (i = 0; i < NUM_OF_PCI_DEVS; i++) { + write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); + + /* If the entry is more than just 0, print it out */ + if(ir->pcidev[i]) { + printk(BIOS_SPEW, " %d: ", i); + for (j = 0; j < 4; j++) { + pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; + printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); + } + printk(BIOS_SPEW, "\n"); + } + } + + /* Route SCI to IRQ9 */ + write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); + + /* Write IRQ assignments to PCI config space */ + write_pci_config_irqs(); +} + +static inline int io_range_in_default(int base, int size) +{ + /* Does it start above the range? */ + if (base >= LPC_DEFAULT_IO_RANGE_UPPER) + return 0; + + /* Is it entirely contained? */ + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && + (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + return 1; + + /* This will return not in range for partial overlaps. */ + return 0; +} + +/* + * Note: this function assumes there is no overlap with the default LPC device's + * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. + */ +static void sc_add_io_resource(device_t dev, int base, int size, int index) +{ + struct resource *res; + + if (io_range_in_default(base, size)) + return; + + res = new_resource(dev, index); + res->base = base; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; +} + +static void sc_add_io_resources(device_t dev) +{ + struct resource *res; + u8 io_index = 0; + + /* + * Add the default claimed IO range for the LPC device + * and mark it as subtractive decode. + */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = LPC_DEFAULT_IO_RANGE_LOWER; + res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* GPIO */ + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); + + /* ACPI */ + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); +} + +static void sc_read_resources(device_t dev) +{ + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + sc_add_mmio_resources(dev); + + /* Add IO resources. */ + sc_add_io_resources(dev); +} + +static void enable_hpet(void) +{ +} + +static void sc_init(struct device *dev) +{ + u32 ibase; + + printk(BIOS_DEBUG, "soc: southcluster_init\n"); + + ibase = pci_read_config32(dev, IBASE) & ~0xF; + + write8(ibase + ILB_MC, 0); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + sc_enable_ioapic(dev); + + sc_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + sc_pirq_init(dev); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + setup_i8259(); + + setup_i8254(); +} + +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disable register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t fd_mask = 0; + uint32_t fd2_mask = 0; + +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + fd_mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + fd2_mask |= name_ ## _DIS + + switch (dev->path.pci.devfn) { + SET_DIS_MASK(MIPI); + break; + SET_DIS_MASK(EMMC); + break; + SET_DIS_MASK(SDIO); + break; + SET_DIS_MASK(SD); + break; + SET_DIS_MASK(SATA); + break; + SET_DIS_MASK(XHCI); + /* Disable super speed PHY when XHCI is not available. */ + fd2_mask |= USH_SS_PHY_DIS; + break; + SET_DIS_MASK(LPE); + break; + SET_DIS_MASK(MMC45); + break; + SET_DIS_MASK(SIO_DMA1); + break; + SET_DIS_MASK(I2C1); + break; + SET_DIS_MASK(I2C2); + break; + SET_DIS_MASK(I2C3); + break; + SET_DIS_MASK(I2C4); + break; + SET_DIS_MASK(I2C5); + break; + SET_DIS_MASK(I2C6); + break; + SET_DIS_MASK(I2C7); + break; + SET_DIS_MASK(TXE); + break; + SET_DIS_MASK(HDA); + break; + SET_DIS_MASK(PCIE_PORT1); + break; + SET_DIS_MASK(PCIE_PORT2); + break; + SET_DIS_MASK(PCIE_PORT3); + break; + SET_DIS_MASK(PCIE_PORT4); + break; + SET_DIS_MASK(EHCI); + break; + SET_DIS_MASK(SIO_DMA2); + break; + SET_DIS_MASK(PWM1); + break; + SET_DIS_MASK(PWM2); + break; + SET_DIS_MASK(HSUART1); + break; + SET_DIS_MASK(HSUART2); + break; + SET_DIS_MASK(SPI); + break; + SET_DIS_MASK2(SMBUS); + break; + SET_DIS_MASK(OTG); + /* Disable OTG PHY when OTG is not available. */ + fd2_mask |= OTG_SS_PHY_DIS; + break; + } + + if (fd_mask != 0) { + write32(func_dis, read32(func_dis) | fd_mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (fd2_mask != 0) { + write32(func_dis2, read32(func_dis2) | fd2_mask); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +/* Parts of the audio subsystem are powered by the HDA device. Therefore, one + * cannot put HDA into D3Hot. Instead perform this workaround to make some of + * the audio paths work for LPE audio. */ +static void hda_work_around(device_t dev) +{ + unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; + + /* Need to set magic register 0x43 to 0xd7 in config space. */ + pci_write_config8(dev, 0x43, 0xd7); + + /* Need to set bit 0 of GCTL to take the device out of reset. However, + * that requires setting up the 64-bit BAR. */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + write32(gctl, read32(gctl) | 0x1); + pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + /* Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. */ + if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { + hda_work_around(dev); + return 0; + } + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ +#define DEV_CASE(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + DEV_CASE(MIPI): + DEV_CASE(SDIO): + DEV_CASE(EMMC): + DEV_CASE(SD): + DEV_CASE(MMC45): + DEV_CASE(LPE): + DEV_CASE(SIO_DMA1): + DEV_CASE(I2C1): + DEV_CASE(I2C2): + DEV_CASE(I2C3): + DEV_CASE(I2C4): + DEV_CASE(I2C5): + DEV_CASE(I2C6): + DEV_CASE(I2C7): + DEV_CASE(SIO_DMA2): + DEV_CASE(PWM1): + DEV_CASE(PWM2): + DEV_CASE(HSUART1): + DEV_CASE(HSUART2): + DEV_CASE(SPI): + DEV_CASE(OTG): + offset = 0x80; + break; + DEV_CASE(SATA): + DEV_CASE(XHCI): + DEV_CASE(EHCI): + offset = 0x70; + break; + DEV_CASE(HDA): + DEV_CASE(SMBUS): + offset = 0x50; + break; + DEV_CASE(TXE): + /* TXE cannot be placed in D3Hot. */ + return 0; + break; + DEV_CASE(PCIE_PORT1): + DEV_CASE(PCIE_PORT2): + DEV_CASE(PCIE_PORT3): + DEV_CASE(PCIE_PORT4): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +static struct device_operations device_ops = { + .read_resources = sc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = NULL, + .init = sc_init, + .enable = southcluster_enable_dev, + .scan_bus = scan_static_bus, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPC_DEVID, +}; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c new file mode 100644 index 0000000..ddec2e0 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is derived from the flashrom project. */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <spi_flash.h> + +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> + +#ifdef __SMM__ +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* !__SMM__ */ + +typedef struct spi_slave ich_spi_slave; + +static int ichspi_lock = 0; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller cntlr; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) + +static u8 readb_(const void *addr) +{ + u8 v = read8((unsigned long)addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = read16((unsigned long)addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = read32((unsigned long)addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, const void *addr) +{ + write8((unsigned long)addr, b); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, const void *addr) +{ + write16((unsigned long)addr, b); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, const void *addr) +{ + write32((unsigned long)addr, b); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ + +#define readb_(a) read8((uint32_t)a) +#define readw_(a) read16((uint32_t)a) +#define readl_(a) read32((uint32_t)a) +#define writeb_(val, addr) write8((uint32_t)addr, val) +#define writew_(val, addr) write16((uint32_t)addr, val) +#define writel_(val, addr) write32((uint32_t)addr, val) + +#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr.bbar); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n"); + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + ich_spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + return NULL; + } + + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + return slave; +} + +static ich9_spi_regs *spi_regs(void) +{ + device_t dev; + uint32_t sbase; + +#ifdef __SMM__ + dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); +#else + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); +#endif + pci_read_config_dword(dev, SBASE, &sbase); + sbase &= ~0x1ff; + + return (void *)sbase; +} + +void spi_init(void) +{ + ich9_spi_regs *ich9_spi = spi_regs(); + + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + ich_set_bbar(0); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + uint16_t optypes; + uint8_t opmenu[cntlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ichspi_lock) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 40000; /* This will result in 400 ms */ + u16 status = 0; + + while (timeout--) { + status = readw_(cntlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr.status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) +{ + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bitsout / 8, + din, bitsin / 8, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bitsout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bitsin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + /* Right now we don't support writing partial bytes. */ + if (bitsout % 8 || bitsin % 8) { + printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + + spi_setup_type(&trans); + if ((opcode_index = spi_setup_opcode(&trans)) < 0) + return -1; + if ((with_address = spi_setup_offset(&trans)) < 0) + return -1; + + if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr.preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr.preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bitesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + goto spi_xfer_exit; + } + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr.databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " CONTROLLER_PAGE_LIMIT?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr.databytes); + else + data_length = min(trans.bytesin, cntlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr.data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr.data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + +spi_xfer_exit: + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr.preop); + + return 0; +} diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c new file mode 100644 index 0000000..b74e41e --- /dev/null +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <baytrail/msr.h> +#if !defined(__PRE_RAM__) +#include <baytrail/ramstage.h> +#else +#include <baytrail/romstage.h> +#endif + +unsigned bus_freq_khz(void) +{ + msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: + return 83333; + case 1: + return 100000; + case 2: + return 133333; + case 3: + return 116666; + default: + return 0; + } +} + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; +} + +#if !defined(__SMM__) + +void set_max_freq(void) +{ + msr_t perf_ctl; + msr_t msr; + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_RATIOS); + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_VIDS); + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + perf_ctl.hi = 0; + + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); +} + +#endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_baytrail/usb.c b/src/soc/intel/fsp_baytrail/usb.c new file mode 100644 index 0000000..fa5adff --- /dev/null +++ b/src/soc/intel/fsp_baytrail/usb.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <device/device.h> + +static const unsigned short pci_device_ids[] = { + XHCI_DEVID, + EHCI_DEVID, + 0, +}; + +static struct device_operations ehci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, /* handled by the FSP */ + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_usb __pci_driver = { + .ops = &ehci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids +}; diff --git a/src/soc/intel/fsp_baytrail/xhci.c b/src/soc/intel/fsp_baytrail/xhci.c new file mode 100644 index 0000000..13b86bc --- /dev/null +++ b/src/soc/intel/fsp_baytrail/xhci.c @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/ramstage.h> +#include <baytrail/xhci.h> + +#include "chip.h" + +struct reg_script usb3_phy_script[] = { + /* USB3PHYInit() */ + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, + ~0x00700000, 0x00500000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, + ~0x001f0000, 0x000A0000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, + ~0x0000000f, 0x0000000b), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, + ~0x000000f0, 0x000000f0), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, + ~0x000001c0, 0x00000000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, + ~0x00000070, 0x00000020), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, + ~0x00000002, 0x00000002), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, + ~0x00000000, 0x00040000), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_script[] = { + /* CommonXhciHcInit() */ + /* BAR + 0x0c[31:16] = 0x0200 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), + /* BAR + 0x0c[7:0] = 0x0a */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), + /* BAR + 0x8094[23,21,14]=111b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), + /* BAR + 0x8110[20,11,8,2]=1100b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), + /* BAR + 0x8144[8,7,6]=111b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), + /* BAR + 0x8154[21,13,3]=010b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), + /* BAR + 0x816c[19:0]=1110x100000000111100b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), + /* BAR + 0x8188[26,24]=11b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), + /* BAR + 0x8174=0x1000c0a*/ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), + /* BAR + 0x854c[29]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), + /* BAR + 0x8178[12:0]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), + /* BAR + 0x8164[7:0]=0xff */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), + /* BAR + 0x0010[10,9,5]=110b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), + /* BAR + 0x8058[20,16,8]=110b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), + /* BAR + 0x8060[25]=1b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), + /* BAR + 0x80f0[20]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), + /* BAR + 0x8008[19]=1b (to enable LPM) */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), + /* BAR + 0x80fc[25]=1b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), + /* 0x40/0x44 are written as bytes to avoid touching bit31 */ + /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ + REG_PCI_RMW8(0x41, ~0x06, 0x01), + /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ + REG_PCI_RMW8(0x42, 0x3c, 0x04), + /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ + REG_PCI_RMW8(0x44, 0x00, 0x8f), + REG_PCI_RMW8(0x45, ~0xcf, 0xc6), + REG_PCI_RMW8(0x46, ~0x0f, 0x0f), + /* BAR + 0x8140 = 0xff00f03c */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_boot_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), + /* BAR + 0x80e0 toggle bit 24=0 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_resume_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), + REG_SCRIPT_END +}; + +const struct reg_script xhci_clock_gating_script[] = { + /* ConfigureXhciClockGating() */ + /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ + REG_PCI_RMW16(0x40, ~0x0600, 0x0100), + REG_PCI_RMW8(0x42, ~0x38, 0x04), + /* D20:F0:44[5:3]=001b */ + REG_PCI_RMW16(0x44, ~0x0030, 0x0008), + /* D20:F0:A0[19:18]=01b */ + REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), + /* D20:F0:A4[15:0]=0x00 */ + REG_PCI_WRITE16(0xa4, 0x0000), + /* D20:F0:B0[21:17,14:13]=0000000b */ + REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), + /* D20:F0:50[31:0]=0x0bce6e5f */ + REG_PCI_WRITE32(0x50, 0x0bce6e5f), + REG_SCRIPT_END +}; + +/* Warm Reset a USB3 port */ +static void xhci_reset_port_usb3(device_t dev, int port) +{ + struct reg_script reset_port_usb3_script[] = { + /* Issue Warm Port Rest to the port */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + XHCI_USB3_PORTSC_WPR), + /* Wait up to 100ms for it to complete */ + REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, + XHCI_RESET_TIMEOUT), + /* Clear change status bits, do not set PED */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), + REG_SCRIPT_END + }; + reg_script_run_on_dev(dev, reset_port_usb3_script); +} + +/* Prepare ports to be routed to EHCI or XHCI */ +static void xhci_route_all(device_t dev) +{ + static const struct reg_script xhci_route_all_script[] = { + /* USB3 SuperSpeed Enable */ + REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), + /* USB2 Port Route to XHCI */ + REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), + REG_SCRIPT_END + }; + u32 port_disabled; + int port; + + printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); + + /* Route ports to XHCI controller */ + reg_script_run_on_dev(dev, xhci_route_all_script); + + if (acpi_slp_type == 3) + return; + + /* Reset enabled USB3 ports */ + port_disabled = pci_read_config32(dev, XHCI_USB3PDO); + for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { + if (port_disabled & (1 << port)) + continue; + xhci_reset_port_usb3(dev, port); + } +} + +static void xhci_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + struct reg_script xhci_hc_init[] = { + /* Initialize clock gating */ + REG_SCRIPT_NEXT(xhci_clock_gating_script), + /* Finalize XHCCI1 and XHCCI2 */ + REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), + REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), + /* Set USB2 Port Routing Mask */ + REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), + /* Set USB3 Port Routing Mask */ + REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), + REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), + REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), + /* Close per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), + REG_SCRIPT_END + }; + + /* Initialize XHCI controller for boot or resume path */ + if (acpi_slp_type == 3) + reg_script_run_on_dev(dev, xhci_init_resume_script); + else + reg_script_run_on_dev(dev, xhci_init_boot_script); + + /* Finalize Initialization */ + reg_script_run_on_dev(dev, xhci_hc_init); + + /* Route all ports to XHCI if requested */ + if (config->usb_route_to_xhci) + xhci_route_all(dev); +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};
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Martin Roth