Patch set updated for coreboot: 86faf54 ibexpeak: Set number of USB ports.

[Vladimir Serbinenko]

Vladimir Serbinenko ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5956

-gerrit

commit 86faf54c3fcfeffd81e09cb29f41259178004db8
Author: Vladimir Serbinenko 
Date:   Sat Jun 7 16:41:14 2014 +0200

ibexpeak: Set number of USB ports.

Change-Id: Ife3febcc88967386dfae624cd237562a34a68471
    Signed-off-by: Vladimir Serbinenko 
---
 src/southbridge/intel/ibexpeak/usb_ehci.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 21a257f..868a068 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -30,6 +30,8 @@
 static void usb_ehci_init(struct device *dev)
 {
    u32 reg32;
+	struct resource *res;
+	u8 access_cntl;

/* Disable Wake on Disconnect in RMH */
    reg32 = RCBA32(0x35b0);
@@ -50,6 +52,21 @@ static void usb_ehci_init(struct device *dev)
    //reg32 |= PCI_COMMAND_SERR;
    pci_write_config32(dev, PCI_COMMAND, reg32);

+	access_cntl = pci_read_config8(dev, 0x80);
+
+	/* Enable writes to protected registers. */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (res) {
+		/* Number of ports and companion controllers.  */
+		reg32 = read32(res->base + 4);
+		write32(res->base + 4, (reg32 & 0xfff00000) | 2);
+	}
+
+	/* Restore protection. */
+	pci_write_config8(dev, 0x80, access_cntl);
+
    printk(BIOS_DEBUG, "done.\n");
 }