Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
soc/intel/skylake: Make TPM reserve area from 20KB to 32KB
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38512/1
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 3902b93..96bfd65 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -182,11 +182,11 @@ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, 0x00000000, PCH_PRESERVED_BASE_SIZE)
- /* TPM Area (0xfed40000-0xfed44fff) */ + /* TPM Area (0xfed40000-0xfed47fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000) + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) })
/* Find PCI resource area in MCRS */
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB Why? Please provide an explanation in the commit description.
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38512
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
soc/intel/skylake: Make TPM reserve area from 20KB to 32KB
The TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000).
For CR50 TPM device the MMIO size requirement is 32KB (0x8000).
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38512/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB
Why? Please provide an explanation in the commit description.
yes, sure
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
Patch Set 2: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG@12 PS2, Line 12: For CR50 TPM device the MMIO size requirement is 32KB (0x8000). Is this the same Cr50 I'm familiar with? i.e. h1? It's not connected on a bus that can memory map anything nor can the hardware support it without an assist from a host controller somewhere else. I'm perplexed by the motivation of this patch.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG@12 PS2, Line 12: For CR50 TPM device the MMIO size requirement is 32KB (0x8000).
Is this the same Cr50 I'm familiar with? i.e. […]
got your point, it like this
1. Since APL onwards all Chrome projects usage H1/Cr50 2. we are reserving 32KB for TPM from the TPM base address 3. Also update the same inside northbridge.asl
looks like these are not even required for TPM_CR50 design, its wrong reservation.
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38512
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device
The TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000).
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38512/3
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG@10 PS3, Line 10: and the size of the MMIO area is 20KB (0x5000). This explains nothing about the actual change.
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50) This is highly irritating. By excluding one case when it is wrong, you make it look like it's correct otherwise. When is this reservation actually correct?
I'm not an expert, but a hunch tells me this should be `#if CONFIG(LPC_TPM)`.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
This is highly irritating. By excluding one case when it is wrong, you make […]
basically this reservation is true for all TPM device using TIS interface using SOC bus like LPC, SPI and I2C as per TPM specification.
As Aaron explained google TPM doesn't even need those SOC mapped memory for its usage. Hence rather keeping
#if CONFIG(LPC_TPM) | CONFIG(SPI_TPM) || CONFIG(I2C_TPM), i have kept !TPM_CR50
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
basically this reservation is true for all TPM device using TIS interface using SOC bus like LPC, SP […]
This is the confusing part: While TIS assumes that a SPI TPM has memory-mapped registers, nothing for coreboot's SPI_TPM or I2C_TPM looks like that would be the case. I guess one would have to attach a TPM to the "Fast SPI" interface of an Intel SoC to get memory-mapping, but that's not supported by SPI_TPM, it seems.
Also, CR50 implies SPI_TPM || I2C_TPM.
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000) All the #if aside, where is it written that the PCH doesn't decode this range when there is no (compatible) TPM attached?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
Patch Set 1 looks good to me btw. (unless the PCH doesn't decode it unconditionally. if it does, we should also reserve the range within coreboot).
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
This is the confusing part: While TIS assumes that a SPI TPM has memory-mapped […]
'#if CONFIG(LPC_TPM)' is not necessarily correct either. I believe we need a semantic that specifically indicates memory mapped TPM that conforms to the PC client TPM spec (didn't want to locate the exact one).
https://trustedcomputinggroup.org/resources/?workgroups=PC%20Client&
However the memory mapped TPM support is provided is actually agnostic to the interconnect. For CR50 purposes, I can confirm it can't be used with current memory mapping assist, and I'm fairly certain we don't implement PC client spec fully.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
'#if CONFIG(LPC_TPM)' is not necessarily correct either. I believe we need a semantic that specifically indicates memory mapped TPM that conforms to the PC client TPM spec (didn't want to locate the exact one).
Yes, if we wanted to advertise memory-mapped TPM support. But isn't it that we advertise here what is decoded (no matter if there is a device behind it)?
For instance, if the PCH does positively decode it, the OS would have to avoid that range for resource allocation. It can only do that if we tell it to.
I couldn't find any clue in the EDS, if the decoding is conditional. Should we risk anything just to make some log look nicer?
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
Patch Set 1 looks good to me btw. (unless the PCH doesn't decode it unconditionally. if it does, we should also reserve the range within coreboot).
But why increase the reservation size? I don't see
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
Yes, if we wanted to advertise memory-mapped TPM support. But isn't it that we advertise here what is decoded (no matter if there is a device behind it)?
For instance, if the PCH does positively decode it, the OS would have to avoid that range for resource allocation. It can only do that if we tell it to.
I couldn't find any clue in the EDS, if the decoding is conditional. Should we risk anything just to make some log look nicer?
Yes, there's currently nothing tying the actual hardware configuration to the advertised resources in ACPI currently. We should probably generate all this on the fly, tbh. I think the decoding is conditional from my recollection (but it might just be HPET that I'm thinking of).
As far as OS assignment, you are correct that the OS needs to avoid that range if the chipset is decoding it since the transaction won't be routed correctly.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
Patch Set 1 looks good to me btw. (unless the PCH doesn't decode it unconditionally. if it does, we should also reserve the range within coreboot).
But why increase the reservation size? I don't see
That detail changed with SKL, see PCH EDS vol1.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
Yes, if we wanted to advertise memory-mapped TPM support. But isn't it that we […]
this MMIO address range is specific for TPM specification and from Intel PCH side, this address doesn't have anything specific hence we might not need to reserve this range from OS space if required TPM support is not there.
I have verified firmware PCH fixed range list for SPT till latest TGP, this ranges doesn't exist in fixed range as expected.
this is what i have found in TPM ACPI spec
The TPM device is defined with ACPI ID "PNP0C31". Platform builds a SSDT and passes it into the guest through the fw_cfg device. The device description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area.
Earlier all chrome supported IA soc till SPT were using non CR50 TPM hence reserving those range make sense but today with CML and WHL, those address doesn't even valid to reserved in chrome platform
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 3: Code-Review+1
Uh, TPM is alien stuff to me. I haven't looked into the details yet, though.
Hello Aaron Durbin, Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38512
to look at the new patch set (#4).
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device
As per PC client TPM specification, the TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed system memory from getting used by OS.
Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence additional reservation might not required.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38512/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG@10 PS3, Line 10: and the size of the MMIO area is 20KB (0x5000).
This explains nothing about the actual change.
Ack
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
this MMIO address range is specific for TPM specification and from Intel PCH side, this address does […]
Ack
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000)
All the #if aside, where is it written that the PCH doesn't decode this range […]
PCH will always decode any valid fixed range memory but as per PCH fixed memory map, i don't see this memory been mentioned
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device
As per PC client TPM specification, the TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed system memory from getting used by OS.
Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence additional reservation might not required.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 3902b93..c4d8a70 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -182,11 +182,13 @@ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, 0x00000000, PCH_PRESERVED_BASE_SIZE)
+#if !CONFIG(TPM_CR50) /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000) +#endif })
/* Find PCI resource area in MCRS */
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
Patch Set 5:
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
I have tested this on EVE, Soraka, Hatch and Icelake RVP
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
Patch Set 5:
Patch Set 5:
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
I have tested this on EVE, Soraka, Hatch and Icelake RVP
btw, i didn't intentionally merge this common CL which has same changes so we are open for discussion still https://review.coreboot.org/c/coreboot/+/38456/14
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
(1 comment)
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
I have tested this on EVE, Soraka, Hatch and Icelake RVP
Just to be sure we're talking about the same thing. Have you tested if a downstream device can decode MMIO in the given range?
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000)
PCH will always decode any valid fixed range memory but as per PCH fixed memory map, i don't see thi […]
Where is this map?
And if it's not fixed, how is it triggered?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 5:
(1 comment)
Patch Set 5:
(1 comment)
Can you please not merge patches in the middle of the discussion? Was this tested at least? I mean real tested, not oops it still boots.
I have tested this on EVE, Soraka, Hatch and Icelake RVP
Just to be sure we're talking about the same thing. Have you tested if a downstream device can decode MMIO in the given range?
For non CR50 TPM, there is a strap setting to tell TPM sitting on which bus, this will help you to decode the range in PCH.
For an example, infinion TPM chip on ICL-RVP, i could see DID/VID in that fixed range where else for H1 TPM, no such valid entries into given fixed range. As Aaron mentioned this address is not required for H1 TPM.
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000)
Where is this map? […]
you can find this fix memory map in FAS document.
-
Aaron Durbin (Code Review) -
Angel Pons (Code Review)
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Nico Huber (Code Review)
-
Subrata Banik (Code Review)