Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74789 )
Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment ......................................................................
soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjustment.
The edp_panel_t9_ms parameter is set for bloff to varybloff.
BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table.
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Reviewed-by: Jason Glenesk jason.glenesk@gmail.com Reviewed-by: Martin Roth martin.roth@amd.corp-partner.google.com Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c 2 files changed, 27 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 5eb7c41..f161038 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -179,6 +179,8 @@
/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ uint8_t edp_panel_t8_ms; + /* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */ + uint8_t edp_panel_t9_ms;
};
diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index cea26a9..6582a7c 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -171,6 +171,7 @@
mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; + mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms;
fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg);