Change in ...coreboot[master]: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30939
Change subject: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
[UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
Not yet tested.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc A src/mainboard/foxconn/d41s/bootblock.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/Makefile.inc A src/mainboard/intel/d510mo/bootblock.c M src/mainboard/intel/d510mo/romstage.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 15 files changed, 149 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/1
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 6566a01..e6e904d 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -20,4 +20,11 @@ hex default 0x4000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e5..c95e135 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/bootblock.c b/src/mainboard/foxconn/d41s/bootblock.c new file mode 100644 index 0000000..86abba4 --- /dev/null +++ b/src/mainboard/foxconn/d41s/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit damien@zamaudio.com + * Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8721f/it8721f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + + /* Environment Controller */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ade85e6..c7e6e55 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -15,31 +15,7 @@ * GNU General Public License for more details. */
-#include <arch/io.h> -#include <device/pnp_def.h> -#include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8721f/it8721f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -}
void get_mb_spd_addrmap(u8 *spd_addrmap) { diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/bootblock.c b/src/mainboard/intel/d510mo/bootblock.c new file mode 100644 index 0000000..b66164e --- /dev/null +++ b/src/mainboard/intel/d510mo/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN + | COMB_LPC_EN); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 28e2e25..d9ec66b 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -14,31 +14,8 @@ * GNU General Public License for more details. */
-#include <arch/io.h> -#include <device/pnp_def.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/winbond/w83627thg/w83627thg.h> -#include <superio/winbond/common/winbond.h> - -#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -}
void mb_pirq_setup(void) { diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305..773f1db 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 524bcae..6323391 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
+bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 1fab845..373d476 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */
#include <arch/io.h> -#define PCIEXBAR 0x60 +#include <cpu/intel/car/bootblock.h> +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1
-static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cf..f53ff17 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u8 decode_pciebar(u32 *const base, u32 *const len);
/* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 10ac0f5..b25c36e 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -55,17 +55,12 @@ if (bist == 0) enable_lapic();
- /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
- mb_enable_lpc(); // nm10_enable_lpc - /* Initialize console device(s) */ console_init();
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..0864786 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 0000000..8b9826a --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/intel/car/bootblock.h> +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30939/1/src/southbridge/intel/i82801gx/bootb... File src/southbridge/intel/i82801gx/bootblock_gcc.c:
https://review.coreboot.org/#/c/30939/1/src/southbridge/intel/i82801gx/bootb... PS1, Line 38: pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); line over 80 characters
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30939
to look at the new patch set (#2).
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc A src/mainboard/foxconn/d41s/bootblock.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/Makefile.inc A src/mainboard/intel/d510mo/bootblock.c M src/mainboard/intel/d510mo/romstage.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 15 files changed, 149 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/30939/2/src/southbridge/intel/i82801gx/bootb... File src/southbridge/intel/i82801gx/bootblock_gcc.c:
https://review.coreboot.org/#/c/30939/2/src/southbridge/intel/i82801gx/bootb... PS2, Line 38: pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); line over 80 characters
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
I just want some discussion here before hitting +2.
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/bootblock... File src/mainboard/foxconn/d41s/bootblock.c:
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/bootblock... PS2, Line 36: | COMA_LPC_EN); I think we should document how much of LPC configuration is to be done in bootblock and whether use of devicetree is allowed/forbidden.
Also, while the file was called romstage.c, there is really no reason why we could not include it for bootblock instead of splitting out the function we know we want? We seem to use prefix early_ for things pre-ram on filenames?
I am happy with what I see here, although we really only need COMA and CNF1 for now. Maybe IO 0x80 with AMD chipsets.
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... File src/mainboard/foxconn/d41s/romstage.c:
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... PS2, Line 27: Speculations, do we want to redo this in romstage? Or complete a minimal configuration (from bootblock) with settings from devicetree?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/bootblock... File src/mainboard/foxconn/d41s/bootblock.c:
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/bootblock... PS2, Line 36: | COMA_LPC_EN);
I think we should document how much of LPC configuration is to be done in bootblock and whether use […]
I don't think it is the case here, but in general you might end up needing to link more than you want in the bootblock just to get a common early_ file to compile even if it does not end up in the binary.
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... File src/mainboard/foxconn/d41s/romstage.c:
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... PS2, Line 27:
Speculations, do we want to redo this in romstage? Or complete a minimal configuration (from bootblo […]
Any downside to enable all default LPC decode ranges in a common place? Haswell does that.
The GENx_DEC should be done using the devicetree probably romstage since some boards set up things like SIO/FANs with it.
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30939
to look at the new patch set (#3).
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc R src/mainboard/foxconn/d41s/early_init.c M src/mainboard/intel/d510mo/Makefile.inc R src/mainboard/intel/d510mo/early_init.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 13 files changed, 79 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/30939/3/src/mainboard/foxconn/d41s/early_ini... File src/mainboard/foxconn/d41s/early_init.c:
https://review.coreboot.org/#/c/30939/3/src/mainboard/foxconn/d41s/early_ini... PS3, Line 33: pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); line over 80 characters
https://review.coreboot.org/#/c/30939/3/src/mainboard/intel/d510mo/early_ini... File src/mainboard/intel/d510mo/early_init.c:
https://review.coreboot.org/#/c/30939/3/src/mainboard/intel/d510mo/early_ini... PS3, Line 34: pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); line over 80 characters
https://review.coreboot.org/#/c/30939/3/src/southbridge/intel/i82801gx/bootb... File src/southbridge/intel/i82801gx/bootblock_gcc.c:
https://review.coreboot.org/#/c/30939/3/src/southbridge/intel/i82801gx/bootb... PS3, Line 38: pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); line over 80 characters
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30939
to look at the new patch set (#4).
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc R src/mainboard/foxconn/d41s/early_init.c M src/mainboard/intel/d510mo/Makefile.inc R src/mainboard/intel/d510mo/early_init.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 13 files changed, 78 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/#/c/30939/4/src/mainboard/intel/d510mo/early_ini... File src/mainboard/intel/d510mo/early_init.c:
https://review.coreboot.org/#/c/30939/4/src/mainboard/intel/d510mo/early_ini... PS4, Line 36: | COMB_LPC_EN); whitespace?
https://review.coreboot.org/#/c/30939/4/src/mainboard/intel/d510mo/early_ini... PS4, Line 43: whitespace?
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30939
to look at the new patch set (#5).
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc R src/mainboard/foxconn/d41s/early_init.c M src/mainboard/intel/d510mo/Makefile.inc R src/mainboard/intel/d510mo/early_init.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 13 files changed, 73 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/30939/5/src/southbridge/intel/i82801gx/bootb... File src/southbridge/intel/i82801gx/bootblock_gcc.c:
https://review.coreboot.org/#/c/30939/5/src/southbridge/intel/i82801gx/bootb... PS5, Line 27: reg8 = pci_read_config8(dev, 0xdc); BIOS_CNTL
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30939
to look at the new patch set (#6).
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc R src/mainboard/foxconn/d41s/early_init.c M src/mainboard/intel/d510mo/Makefile.inc R src/mainboard/intel/d510mo/early_init.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 13 files changed, 71 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/6
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... File src/mainboard/foxconn/d41s/romstage.c:
https://review.coreboot.org/#/c/30939/2/src/mainboard/foxconn/d41s/romstage.... PS2, Line 27:
Any downside to enable all default LPC decode ranges in a common place? Haswell does that.
No downsides afaict, as long as the allocator is made aware.
Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30939 )
Change subject: nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc R src/mainboard/foxconn/d41s/early_init.c M src/mainboard/intel/d510mo/Makefile.inc R src/mainboard/intel/d510mo/early_init.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 13 files changed, 71 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index b1b310d..d3af4ca 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -21,4 +21,11 @@ hex default 0x4000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e5..c95e135 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76..057b5bf 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,4 @@ +romstage-y += early_init.c +bootblock-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/early_init.c similarity index 94% rename from src/mainboard/foxconn/d41s/romstage.c rename to src/mainboard/foxconn/d41s/early_init.c index cdd12dc..6568d96 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */
+#include <bootblock_common.h> #include <device/pci_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> @@ -23,7 +24,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
-void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76..f87689b 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,4 @@ +bootblock-y += early_init.c +romstage-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/early_init.c similarity index 95% rename from src/mainboard/intel/d510mo/romstage.c rename to src/mainboard/intel/d510mo/early_init.c index 024c3e1..2719e87 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <bootblock_common.h> #include <device/pci_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0)
-void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 1878cc4..2b4f502 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -33,6 +33,7 @@ select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 90a9f48..c72fe3e 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
+bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd76fb9..bd510b0 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */
#include <device/pci_ops.h> -#define PCIEXBAR 0x60 +#include <cpu/intel/car/bootblock.h> +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1
-static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cf..f53ff17 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u8 decode_pciebar(u32 *const base, u32 *const len);
/* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 41fb0f6..8d7de45 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -57,20 +57,12 @@ if (bist == 0) enable_lapic();
- /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
- mb_enable_lpc(); // nm10_enable_lpc - - /* Initialize console device(s) */ - console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist);
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 32a4bf5..6e7f9bf 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 0000000..9967888 --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, BIOS_CNTL); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, BIOS_CNTL, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +}
-
Arthur Heymans (Code Review) -
build bot (Jenkins) (Code Review)
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Kyösti Mälkki (Code Review)
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Nico Huber (Code Review)
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Patrick Rudolph (Code Review)