Change in coreboot[master]: soc/amd/cezanne: factor out AOAC offset defines

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55533 )

Change subject: soc/amd/cezanne: factor out AOAC offset defines
......................................................................

soc/amd/cezanne: factor out AOAC offset defines

Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.

Signed-off-by: Felix Held 
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
---
M src/soc/amd/cezanne/aoac.c
A src/soc/amd/cezanne/include/soc/aoac_defs.h
M src/soc/amd/cezanne/include/soc/southbridge.h
M src/soc/amd/cezanne/uart.c
4 files changed, 23 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/55533/1

diff --git a/src/soc/amd/cezanne/aoac.c b/src/soc/amd/cezanne/aoac.c
index 9c58bb5..c313a55 100644
--- a/src/soc/amd/cezanne/aoac.c
+++ b/src/soc/amd/cezanne/aoac.c
@@ -3,6 +3,7 @@
 #include <stdint.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/aoac.h>
+#include <soc/aoac_defs.h>
 #include <soc/southbridge.h>
 #include <delay.h>

diff --git a/src/soc/amd/cezanne/include/soc/aoac_defs.h b/src/soc/amd/cezanne/include/soc/aoac_defs.h
new file mode 100644
index 0000000..5309cb0
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/aoac_defs.h
@@ -0,0 +1,21 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_AOAC_DEFS_H
+#define AMD_CEZANNE_AOAC_DEFS_H
+
+/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
+#define FCH_AOAC_DEV_CLK_GEN		0
+#define FCH_AOAC_DEV_I2C0		5
+#define FCH_AOAC_DEV_I2C1		6
+#define FCH_AOAC_DEV_I2C2		7
+#define FCH_AOAC_DEV_I2C3		8
+#define FCH_AOAC_DEV_I2C4		9
+#define FCH_AOAC_DEV_I2C5		10
+#define FCH_AOAC_DEV_UART0		11
+#define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_AMBA		17
+#define FCH_AOAC_DEV_ESPI		27
+#define FCH_AOAC_DEV_EMMC		28
+
+#endif /* AMD_CEZANNE_AOAC_DEFS_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index f90964b..0ed5f33 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -105,20 +105,6 @@
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)

-/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
-#define FCH_AOAC_DEV_CLK_GEN		0
-#define FCH_AOAC_DEV_I2C0		5
-#define FCH_AOAC_DEV_I2C1		6
-#define FCH_AOAC_DEV_I2C2		7
-#define FCH_AOAC_DEV_I2C3		8
-#define FCH_AOAC_DEV_I2C4		9
-#define FCH_AOAC_DEV_I2C5		10
-#define FCH_AOAC_DEV_UART0		11
-#define FCH_AOAC_DEV_UART1		12
-#define FCH_AOAC_DEV_AMBA		17
-#define FCH_AOAC_DEV_ESPI		27
-#define FCH_AOAC_DEV_EMMC		28
-
 void fch_pre_init(void);
 void fch_early_init(void);
 void fch_init(void *chip_info);
diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c
index 6c82f1a..212f365 100644
--- a/src/soc/amd/cezanne/uart.c
+++ b/src/soc/amd/cezanne/uart.c
@@ -7,6 +7,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/mmio.h>
+#include <soc/aoac_defs.h>
 #include <soc/gpio.h>
 #include <soc/southbridge.h>
 #include <soc/uart.h>