[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Paul Menzel (Code Review)]

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Tarun, Utkarsh H Patel.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )

Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
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Patch Set 6:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78163/comment/f2347cc1_f82f1744 :
PS6, Line 14: 
Please mention the datasheet name and revision.

File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl:

https://review.coreboot.org/c/coreboot/+/78163/comment/0512bbf3_ae1c7fa6 :
PS6, Line 54: Offset(0xBA8),  /* 0xBA8, MPC - Miscellaneous Port Configuration Register */
            : 	, 30,
            : 	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
            : 	PMEX, 1,       /* 31,  Power Management SCI Enable */
            : 	Offset(0xBB2),  /* 0xBB2, RPPGEN - Root Port Power Gating Enable */
            : 	, 2,
            : 	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
            : 	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
In Gerrit, the `/*` are not correctly aligned with line 53.

https://review.coreboot.org/c/coreboot/+/78163/comment/caa3a6fc_6085b5b1 :
PS6, Line 70: 	Offset(0xBAC),  /* 0xBAC, SMSCS - SMI/SCI Status Register */
Please align `/*`.

https://review.coreboot.org/c/coreboot/+/78163/comment/6efe7499_58279ff0 :
PS6, Line 67: #if CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON)
            : 	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
            : #else
            : 	Offset(0xBAC),  /* 0xBAC, SMSCS - SMI/SCI Status Register */
            : #endif
Maybe define a macro for SMSCS?