[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph, Subrata Banik, Tarun Tuli.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76687?usp=email )

Change subject: soc/intel/alderlake: Disable PCIe clock gating
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Patch Set 3: Code-Review+1

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/76687/comment/197d7f57_8839eaad :
PS1, Line 923: #if CONFIG(FSP_TYPE_IOT)
> It has the same UPDs, but it haven't been updated yet, thus the UPD is still missing.

Huh, not fully awake yet... So, Client FSP doesn't have these UPDs yet? If so, this can be resolved.