[XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB - coreboot-gerrit

27 Feb 2025


      Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune.
Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86582?usp=email )
Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/lpc/lpc_util.c:
https://review.coreboot.org/c/coreboot/+/86582/comment/21b1c72d_5d3b9901?usp... :
PS1, Line 284: 		pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00);
...
nit: […]
Done
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Gerrit-Change-Number: 86582
Gerrit-PatchSet: 2
Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com
Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Fred Reitberger reitbergerfred@gmail.com
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