Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408 --- M src/mainboard/pcengines/apu2/mptable.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39702/1
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 36bd340..747e777 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -15,6 +15,7 @@ #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <stdint.h> +#include <northbridge/amd/pi/nb_common.h> #include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v) @@ -50,6 +51,11 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+ ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); + ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF); + + smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/mptable.c:
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... PS1, Line 54: ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); nit: if you add an extra space before the equals sign, the two lines get aligned
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/mptable.c:
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... PS1, Line 54: ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
nit: if you add an extra space before the equals sign, the two lines get aligned
I think, that is good for macros but not for normal assignments.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
Patch Set 1:
(1 comment)
no need to tweak too in manual formatting when we want to encourage clang-format in the long run ;-)
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu2/mptable.c:
https://review.coreboot.org/c/coreboot/+/39702/1/src/mainboard/pcengines/apu... PS1, Line 54: ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
I think, that is good for macros but not for normal assignments.
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39702 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/pcengines/apu2/mptable.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 36bd340..747e777 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -15,6 +15,7 @@ #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <stdint.h> +#include <northbridge/amd/pi/nb_common.h> #include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v) @@ -50,6 +51,11 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+ ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); + ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF); + + smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
Patch Set 2:
Patch Set 1:
(1 comment)
no need to tweak too in manual formatting when we want to encourage clang-format in the long run ;-)
Ah, I forget about automatic formatting. I understand that such a small case isn't worth it, but could we please have some mercy for the table-like files? 😜
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39702 )
Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1641 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1640 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1639 Non-emulation targets: HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1643 HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : FAIL : https://lava.9esec.io/r/1642
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Michał Żygowski (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)