Change in coreboot[master]: mb/intel/jasperlake_rvp: Update JSLRVP USB configuration

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39403 )

Change subject: mb/intel/jasperlake_rvp: Update JSLRVP USB configuration
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mb/intel/jasperlake_rvp: Update JSLRVP USB configuration

Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.

Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya 
Reviewed-by: Aamir Bohra 
Reviewed-by: Maulik V Vaghela 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 13 insertions(+), 25 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aamir Bohra: Looks good to me, approved
  V Sowmya: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index e8fc451..f591504 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -30,22 +30,20 @@
    register "DdiPortBDdc" = "1"
    register "DdiPortCDdc" = "1"

-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Bluetooth
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# Type-C Port1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"	# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# Type-C Port3
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"	# Type-C Port4
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port1
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"		# USB2 Type A port1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port2
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# USB2 Type A port2
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Bluetooth
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC2)"		# USB2 Type A port3
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port4

-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WLAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# USB3 WWAN
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"	# UNUSED
    register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED

# Enable Pch iSCLK
@@ -196,16 +194,6 @@
    					device usb 2.7 on end
    				end
    				chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.8 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.9 on end
-					end
-					chip drivers/usb/acpi
    					register "desc" = ""USB3/2 Type-A Left Lower""
    					register "type" = "UPC_TYPE_A"
    					device usb 3.0 on end