Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- A src/soc/intel/baytrail/include/soc/modphy.h M src/soc/intel/baytrail/refcode.c 2 files changed, 785 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/1
diff --git a/src/soc/intel/baytrail/include/soc/modphy.h b/src/soc/intel/baytrail/include/soc/modphy.h new file mode 100644 index 0000000..30df97a --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/modphy.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MODPHY_H_ +#define _MODPHY_H_ + +static u32 baytrail_modphy_table[] = { + 0x000000a6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002208, 0xfffffff3, 0x00000008, 0x00000000, 0x00000001, + 0x000000a3, 0x00002408, 0xfffffff3, 0x00000008, 0x00000000, 0x00000001, + 0x000000a3, 0x00002238, 0xfffffff8, 0x00000006, 0x00000000, 0x00000001, + 0x000000a3, 0x00002438, 0xfffffff8, 0x00000006, 0x00000000, 0x00000001, + 0x000000a3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080a4, 0xffff0000, 0x0000f487, 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0x00000000, 0x00000001, + 0x000000a6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008068, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008068, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008100, 0xfffffffc, 0x00000003, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a6, 0x00000314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000714, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000914, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002318, 0x0000ffff, 0x45140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0x80ffffff, 0x02000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002304, 0xff80ffff, 0x00020000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x000000a3, 0x00002518, 0x0000ffff, 0x47140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0x80ffffff, 0x04000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002504, 0xff80ffff, 0x00040000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, + 0x00000043, 0x00004100, 0xfff00000, 0x0004fa01, 0x00000006, 0x00000007, + 0x00000043, 0x00004200, 0xfff00000, 0x0004ea01, 0x00000006, 0x00000007, + 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004122, 0x00000000, 0x00004011, 0x00000006, 0x00000007, + 0x00000043, 0x00004222, 0x00000000, 0x06004015, 0x00000006, 0x00000007, + 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x000000a6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, +}; + +#define BAYTRAIL_MODPHY_ENTRY_LEN 6 + +#define BAYTRAIL_MODPHY_REVB_OFFSET 0 +#define BAYTRAIL_MODPHY_REVB_ENTRIES 331 + +#define BAYTRAIL_MODPHY_REVA_OFFSET 1986 +#define BAYTRAIL_MODPHY_REVA_ENTRIES 218 + +#define BAYTRAIL_MODPHY_REVB_OFFSET2 3294 +#define BAYTRAIL_MODPHY_REVB_ENTRIES2 6 + +#endif diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 297ed9c..e99a9be 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,15 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> +#include <soc/ramstage.h> +#include <soc/modphy.h> + +#if 0 + +#include <acpi/acpi.h> +#include <cbmem.h> #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> - -#include <soc/ramstage.h> #include <soc/efi_wrapper.h>
static void ABI_X86 send_to_console(unsigned char b) @@ -81,3 +84,206 @@ return; } } + +#endif + +static u8 mmio_read_8(u32 addr) +{ + return *(u8 *) addr; +} + +static u32 mmio_read_32(u32 addr) +{ + return *(u32 *) addr; +} + +static void mmio_write_32(u32 addr, u32 val) +{ + *(u32 *) addr = val; +} + +static void mmio_or_32(u32 addr, u32 val) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, tmp | val); +} + +static void mmio_and_32(u32 addr, u32 val) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, tmp & val); +} + +static void mmio_andor_32(u32 addr, u32 val1, u32 val2) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, (tmp & val1) | val2); +} + +static u8 soc_stepping_table[] = + { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; + +#define SOC_STEPPING_UNKNOWN 7 + +static int get_soc_stepping(void) +{ + u8 idx; + + idx = mmio_read_8(0xE00F8008) - 1; + return idx < ARRAY_SIZE(soc_stepping_table) ? + soc_stepping_table[idx] : SOC_STEPPING_UNKNOWN; +} + +static void program_modphy_table(u32 *table, u32 entries) +{ + u32 tmp; + + for (; entries; --entries, table += BAYTRAIL_MODPHY_ENTRY_LEN) { + mmio_write_32(0xE00000D8, table[1] & 0xffffff00); + mmio_write_32(0xE00000D0, 0xf0 + | ((table[1] & 0xff) << 8) + | ((table[0] & 0xff) << 16) + | ((table[4] & 0xff) << 24)); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, table[1] & 0xffffff00); + mmio_write_32(0xE00000D4, (tmp & table[2]) | table[3]); + mmio_write_32(0xE00000D0, 0xf0 + | ((table[1] & 0xff) << 8) + | ((table[0] & 0xff) << 16) + | ((table[5] & 0xff) << 24)); + } +} + +static inline u64 rdtsc64(void) +{ + struct tsc_struct tscval; + + tscval = rdtsc(); + return (u64) tscval.hi << 32 | (u64) tscval.lo; +} + +static void delay_usecs(u64 usecs) +{ + u64 needed_ticks, start_ticks; + + needed_ticks = usecs * tsc_freq_mhz(); + start_ticks = rdtsc64(); + while (start_ticks - rdtsc64() < needed_ticks) + ; +} + +static void do_magic_writes(void) +{ + mmio_or_32(0xFED0C698, 1); + mmio_or_32(0xFED0C698, 4); + mmio_and_32(0xFED0C698, 0xFFFFFFFD); + mmio_and_32(0xFED0C690, 0xFFFFFFF8); + delay_usecs(100); + mmio_and_32(0xFED0C698, 0xFFFFFFFE); + delay_usecs(100); + mmio_write_32(0xFED0C830, 0x78480); + delay_usecs(40); + mmio_write_32(0xFED0C830, 0x78080); + mmio_or_32(0xFED0C698, 1); + delay_usecs(100); + mmio_or_32(0xFED0C698, 2); + mmio_and_32(0xFED0C698, 0xFFFFFFFB); + mmio_andor_32(0xFED0C690, 0xFFFFFFF8, 1); +} + +static void do_magic_writes2(void) +{ + u32 tmp; + + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x10030BF0); + tmp = mmio_read_32(0x0E00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); + + mmio_write_32(0xE00000D0, 0x11030BF0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100021F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x80000100); + + mmio_write_32(0xE00000D0, 0x110021F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100060F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); + + mmio_write_32(0xE00000D0, 0x110060F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100841F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); + + mmio_write_32(0xE00000D0, 0x110841F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, 0x70008); + mmio_write_32(0xE00000D0, 0x110843F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100203F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x110430); + + mmio_write_32(0xE00000D0, 0x110203F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x110204F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x40010); + mmio_write_32(0xE00000D0, 0x110204F0); +} + +/* + * Replacment for refcode.elf + */ +void baytrail_run_reference_code(void) +{ + int stepping, pollcnt; + u32 addr, val; + + printk(BIOS_DEBUG, "refcode entry\n"); + + stepping = get_soc_stepping(); + if (stepping > 1) { + printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n"); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVB_OFFSET2, + BAYTRAIL_MODPHY_REVB_ENTRIES2); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVB_OFFSET, + BAYTRAIL_MODPHY_REVB_ENTRIES); + } else { + printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n"); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVA_OFFSET, + BAYTRAIL_MODPHY_REVA_ENTRIES); + } + + addr = (mmio_read_32(0xE00F8044) & 0xFFFFFE00) + 0xB0; + mmio_or_32(addr, 8); + for (pollcnt = 0; pollcnt < 10; ++pollcnt) { + val = mmio_read_32(addr); + printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", val); + if (!(val & 8)) + break; + } + + do_magic_writes(); + do_magic_writes2(); + + printk(BIOS_DEBUG, "refcode exit\n"); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode.c:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 130: { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; that open brace { should be on the previous line
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 1: Code-Review+1
(34 comments)
Good work!
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy.h:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... PS1, Line 6: static u32 baytrail_modphy_table[] = { See `src/northbridge/intel/sandybridge/raminit_tables.h` and `src/northbridge/intel/sandybridge/raminit_tables.c` as an example. Placing definitions in headers is a bit troublesome, IIRC the reasons are in CB:34876 review messages.
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... PS1, Line 566: #define BAYTRAIL_MODPHY_REVB_OFFSET 0 I'd split the very large array in smaller arrays instead
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode.c:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 9: #if 0 Instead of preprocessor, I'd have two different files and choose which one to build depending on whether the refcode binary was added to the build or not (there's a Kconfig option for that)
Sandy Bridge does something like it to choose between native raminit and MRC raminit, you can take it as an example.
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 90: static u8 mmio_read_8(u32 addr) read8
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 95: static u32 mmio_read_32(u32 addr) read32
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 100: static void mmio_write_32(u32 addr, u32 val) write32
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 121: val2 I'd rename this: or, data
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 121: val1 I'd rename this: and, mask
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 129: static u8 soc_stepping_table[] = const?
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 138: 0xE00F8008 That's something that falls into the PCI config space. 0xe0000000 is the value of MMCONF_BASE_ADDRESS on baytrail. Looks like this is PCI bus:dev.func 0:31.0 (LPC) offset 0x8, which you can replace with:
pci_read_config8(pcidev_on_root(31, 0), 0x8)
Note that the datasheet says this value can be zero, so subtracting one can result in an underflow.
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 143: static void program_modphy_table(u32 *table, u32 entries) See "Message Bus Register Access" section on the datasheet. Then read my suggestions and compare them against what iosf.c does
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 148: mmio_write_32(0xE00000D8, table[1] & 0xffffff00); This is writing MCRX on PCI bus:dev.func 0:0.0 (SoC Transaction Router):
pci_write_config32(pcidev_on_root(0, 0), 0xd8, table[1] & 0xffffff00);
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 149: mmio_write_32(0xE00000D0, 0xf0 : | ((table[1] & 0xff) << 8) : | ((table[0] & 0xff) << 16) : | ((table[4] & 0xff) << 24)); Same story here, but with MCR:
pci_write_config32(pcidev_on_root(0, 0), 0xd0, (0xf << 4) | /* WR Byte Enable */ ((table[1] & 0xff) << 8) | /* Address Offset */ ((table[0] & 0xff) << 16) | /* Message Port */ ((table[4] & 0xff) << 24)); /* Message Opcode */
Also, you can avoid the masks if you define a struct for each line with u8 values.
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 153: tmp = mmio_read_32(0xE00000D4) Now we read MDR:
tmp = pci_read_config32(pcidev_on_root(0, 0), 0xd0);
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 155: table[3] This can be called `value`
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 155: table[2] This should be called `mask` (you can put names if you use a struct instead of a 2D array)
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 157: table[1] Call this `offset`
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 158: table[0] Call this `port`
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 159: table[5] Call this `opcode`
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 171: static void delay_usecs(u64 usecs) udelay
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 181: do_magic_writes gpio_sc_sdcard_workaround
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 182: { 0xfed0c0000 is "IO_BASE_ADDRESS" and in this case is used to poke some GPIO_SCORE registers. I'll explain that later (need to understand this better). In any case, you can add this comment:
/* Workaround for sighting #4684039 */
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 200: do_magic_writes2 ssa_safe_config
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 203: These are message bus operations, all but one are and-or operations.
Also, writes to 0xd0 signals the end of a message bus read or write. However, you've grouped the writes so that the last write to 0xd0 is at the beginning of the next group, which makes it harder to notice that the two writes to 0xd0 of an and-or RMW operation are almost the same (only differ in the read/write opcode)
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 204: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x10030BF0); : tmp = mmio_read_32(0x0E00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); : : mmio_write_32(0xE00000D0, 0x11030BF0); Port 0x03, Offset 0x0b = BUNIT_BALIMIT0
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 211: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100021F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x80000100); : : mmio_write_32(0xE00000D0, 0x110021F0); Port 0x00, Offset 0x21 = AUNIT_AVCCTL
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 218: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100060F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); : : mmio_write_32(0xE00000D0, 0x110060F0); Port 0x00, Offset 0x60 = AUNIT_ACFCACV
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 225: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100841F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); : : mmio_write_32(0xE00000D0, 0x110841F0); Port 0x08, Offset 0x41 = CUNIT_ACCESS_CTRL_VIOL
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 232: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, 0x70008); : mmio_write_32(0xE00000D0, 0x110843F0); These three lines are different: instead of a and-or RMW operation, it's just a direct write. So, separate them here.
Port 0x08, Offset 0x43 = CUNIT_SSA_REGIONAL_TRUNKGATE_CTL
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 235: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100203F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x110430); : : mmio_write_32(0xE00000D0, 0x110203F0); Port 0x02, Offset 0x03 = TUNIT_CTL
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 242: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x110204F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x40010); : mmio_write_32(0xE00000D0, 0x110204F0); Port 0x02, Offset 0x04 = TUNIT_MISC_CTL
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 276: 0xB0 R_PCH_PMC_MTPMC1
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 276: mmio_read_32(0xE00F8044) Another PCI operation!
pci_read_config32(pcidev_on_root(31, 0), 0x44))
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 280: printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", val); btw, this looks wrong
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/2/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode.c:
https://review.coreboot.org/c/coreboot/+/43133/2/src/soc/intel/baytrail/refc... PS2, Line 130: { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; that open brace { should be on the previous line
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#3).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 6 files changed, 802 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... PS3, Line 48: { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; that open brace { should be on the previous line
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... PS4, Line 48: { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; that open brace { should be on the previous line
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/Kcon... File src/soc/intel/baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/Kcon... PS4, Line 137: "Disable native high-speed PHY init" Maybe:
"Use a binary refcode blob instead of native ModPHY init"
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... File src/soc/intel/baytrail/modphy_table.c:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... PS4, Line 206: 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, : 0x00000043, 0x00004100, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004200, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, These entries are for B0 or later, and are the workaround for USB-related problems, sightings #4376904, #4682850, #4753319
You can add a comment right above this section
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... PS4, Line 547: 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, : 0x00000043, 0x00004100, 0xfff00000, 0x0004fa01, 0x00000006, 0x00000007, : 0x00000043, 0x00004200, 0xfff00000, 0x0004ea01, 0x00000006, 0x00000007, : 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004122, 0x00000000, 0x00004011, 0x00000006, 0x00000007, : 0x00000043, 0x00004222, 0x00000000, 0x06004015, 0x00000006, 0x00000007, : 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, These entries are for A0 only, and are the workaround for USB-related problems, sightings #4376904, #4682850, #4753319
You can add a comment right above this section
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/modp... File src/soc/intel/baytrail/modphy_table.c:
PS3: This table should make use of the existing IOSF infrastructure in coreboot. For instance, the first column seems to be a port number, the second the register offset. The last two columns are opcodes for read and write (the latter is always just `read | 1`). Didn't check in detail, but I guess the other two columns are mask + value for a read-modify-write.
If there are no existing functions for all the ports used here, I'd suggest to deflate the table a little. For instance, port and (read)opcode could be combined into one 16-bit word (write opcode doesn't need a column because we know it's read | 1), register offsets seem to be 16-bit wide too. Overall, that could cut the table size in half.
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... PS3, Line 8: static u8 mmio_read_8(u32 addr) : { : return *(u8 *) addr; : } : : static u32 mmio_read_32(u32 addr) : { : return *(u32 *) addr; : } : : static void mmio_write_32(u32 addr, u32 val) : { : *(u32 *) addr = val; : } : : static void mmio_or_32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, tmp | val); : } : : static void mmio_and_32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, tmp & val); : } : : static void mmio_andor_32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, (tmp & val1) | val2); : } : Please use `#include <device/mmio.h>` instead. It also draws in <arch/mmio.h> i.e. `src/arch/x86/include/arch/mmio.h`.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43133/4//COMMIT_MSG@10 PS4, Line 10: What should be done with all the magic numbers? They aren't magic if they appear on document #538136 (atom e3800 datasheet) 😄
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/modp... File src/soc/intel/baytrail/modphy_table.c:
PS3:
This table should make use of the existing IOSF infrastructure in coreboot. […]
The first column is the IOSF-SB port (8-bit value), the second value is the offset (not sure of its size), the third column is an and-mask, the fourth one is the or-value and the last two columns are read and write opcodes (which only depend on the IOSF-SB port being accessed). I'd define a struct:
struct baytrail_modphy_entry { uint8_t port; uint32_t offset; /* or uint16_t, need to check */ uint32_t mask; uint32_t or; };
And then determine the opcodes depending on the IOSF port.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... PS4, Line 140: | &
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... PS4, Line 147: | &
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#5).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 807 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy_table.h:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 15: #define MODPHY_ENTRY_END (struct modphy_entry) { 0, 0, 0, 0, 0, 0 } Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 47: #define IOSF_READ(op_read, port) \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 49: #define IOSF_WRITE(op_write, port) \ Macros with complex values should be enclosed in parentheses
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 5:
(11 comments)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/iosf.h:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 97: align with tabs?
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 114: 0xa3 0xa6
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy_table.h:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 17: reva a0
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 18: revb b0
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 47: #define IOSF_READ(op_read, port) \
Macros with complex values should be enclosed in parentheses
Please fix this, it can bite you
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 84: 1 This will make more sense if you use shifts:
(1 << 0)
Or, the BIT(x) macro:
BIT(0)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 85: 4 (1 << 2)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 86: 0xFFFFFFFD ~(1 << 1)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 87: 0xFFFFFFF8 ~(1 << 3)
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 114: iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); How about adding and-or functions?
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 137: Replacment Replacement
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
Patch Set 5:
(3 comments)
Nice work!
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 13: static u32 mmio_read32(u32 addr) : { : return *(u32 *) addr; : } : : static void mmio_write32(u32 addr, u32 val) : { : *(u32 *) addr = val; : } : : static void mmio_or32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, tmp | val); : } : : static void mmio_and32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, tmp & val); : } : : static void mmio_andor32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, (tmp & val1) | val2); : } please use arch/mmio.h
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 64: static inline u64 rdtsc64(void) : { : struct tsc_struct tscval; : : tscval = rdtsc(); : return (u64) tscval.hi << 32 | (u64) tscval.lo; : } : : static void udelay(u64 usecs) : { : u64 needed_ticks, start_ticks; : : needed_ticks = usecs * tsc_freq_mhz(); : start_ticks = rdtsc64(); : while (start_ticks - rdtsc64() < needed_ticks) : ; : } Please use delay.h
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 144: printk(BIOS_DEBUG, "refcode entry\n"); Given that this is coreboot and not the refcode, you might want a different message?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#6).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 808 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#7).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 783 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#8).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 783 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#9).
Change subject: baytrail RFC: native replacement for refcode.elf ......................................................................
baytrail RFC: native replacement for refcode.elf
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access?
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 783 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#10).
Change subject: soc/baytrail: Add native refcode replacement ......................................................................
soc/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 783 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/10
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/baytrail: Add native refcode replacement ......................................................................
Patch Set 10:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 50: table->reg); Does this fit into 96 characters?
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 116: int Please use `size_t` or `unsigned int`.
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 118: printk(BIOS_DEBUG, "ModPHY init entry\n"); It’d be great if you also added timestamps for running the ref code.
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 126: "SOC B0 and later ModPhy Table programming\n"); Does this fit into 96 characters?
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 135: "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp); Does this fit into 96 characters?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#11).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 783 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/11
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#12).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 779 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/12
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 12:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 50: table->reg);
Does this fit into 96 characters?
Done
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 116: int
Please use `size_t` or `unsigned int`.
Done
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 126: "SOC B0 and later ModPhy Table programming\n");
Does this fit into 96 characters?
Done
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 135: "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp);
Does this fit into 96 characters?
Done
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/ref... PS12, Line 15: static void mmio_or32(u32 addr, u32 val) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, tmp | val); : } : : static void mmio_and32(u32 addr, u32 val) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, tmp & val); : } : : static void mmio_andor32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, (tmp & val1) | val2); : } please use clrsetbitxx, setbitxx and clrbitxx from include/device/mmio.h
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 12:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... File src/soc/intel/baytrail/include/soc/modphy_table.h:
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 7: u32 u8
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 11: u32 u8
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 12: u32 u8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#13).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 755 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/13
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... File src/soc/intel/baytrail/include/soc/modphy_table.h:
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 7: u32
u8
Done
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 11: u32
u8
Done
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/inc... PS12, Line 12: u32
u8
Done
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/12/src/soc/intel/baytrail/ref... PS12, Line 15: static void mmio_or32(u32 addr, u32 val) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, tmp | val); : } : : static void mmio_and32(u32 addr, u32 val) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, tmp & val); : } : : static void mmio_andor32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = read32((char *) addr); : write32((char *) addr, (tmp & val1) | val2); : }
please use clrsetbitxx, setbitxx and clrbitxx from include/device/mmio. […]
Done
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 13:
(32 comments)
Patch Set 1: Code-Review+1
(34 comments)
Good work!
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy.h:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... PS1, Line 6: static u32 baytrail_modphy_table[] = {
See `src/northbridge/intel/sandybridge/raminit_tables. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode.c:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 9: #if 0
Instead of preprocessor, I'd have two different files and choose which one to build depending on whe […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 90: static u8 mmio_read_8(u32 addr)
read8
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 95: static u32 mmio_read_32(u32 addr)
read32
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 100: static void mmio_write_32(u32 addr, u32 val)
write32
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 121: val1
I'd rename this: and, mask
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 121: val2
I'd rename this: or, data
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 129: static u8 soc_stepping_table[] =
const?
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 138: 0xE00F8008
That's something that falls into the PCI config space. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 143: static void program_modphy_table(u32 *table, u32 entries)
See "Message Bus Register Access" section on the datasheet. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 148: mmio_write_32(0xE00000D8, table[1] & 0xffffff00);
This is writing MCRX on PCI bus:dev.func 0:0.0 (SoC Transaction Router): […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 149: mmio_write_32(0xE00000D0, 0xf0 : | ((table[1] & 0xff) << 8) : | ((table[0] & 0xff) << 16) : | ((table[4] & 0xff) << 24));
Same story here, but with MCR: […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 153: tmp = mmio_read_32(0xE00000D4)
Now we read MDR: […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 155: table[3]
This can be called `value`
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 155: table[2]
This should be called `mask` (you can put names if you use a struct instead of a 2D array)
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 157: table[1]
Call this `offset`
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 158: table[0]
Call this `port`
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 159: table[5]
Call this `opcode`
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 171: static void delay_usecs(u64 usecs)
udelay
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 181: do_magic_writes
gpio_sc_sdcard_workaround
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 182: {
0xfed0c0000 is "IO_BASE_ADDRESS" and in this case is used to poke some GPIO_SCORE registers. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 200: do_magic_writes2
ssa_safe_config
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 203:
These are message bus operations, all but one are and-or operations. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 204: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x10030BF0); : tmp = mmio_read_32(0x0E00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); : : mmio_write_32(0xE00000D0, 0x11030BF0);
Port 0x03, Offset 0x0b = BUNIT_BALIMIT0
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 211: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100021F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x80000100); : : mmio_write_32(0xE00000D0, 0x110021F0);
Port 0x00, Offset 0x21 = AUNIT_AVCCTL
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 218: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100060F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); : : mmio_write_32(0xE00000D0, 0x110060F0);
Port 0x00, Offset 0x60 = AUNIT_ACFCACV
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 225: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100841F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); : : mmio_write_32(0xE00000D0, 0x110841F0);
Port 0x08, Offset 0x41 = CUNIT_ACCESS_CTRL_VIOL
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 232: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, 0x70008); : mmio_write_32(0xE00000D0, 0x110843F0);
These three lines are different: instead of a and-or RMW operation, it's just a direct write. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 235: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x100203F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x110430); : : mmio_write_32(0xE00000D0, 0x110203F0);
Port 0x02, Offset 0x03 = TUNIT_CTL
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 242: mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D0, 0x110204F0); : tmp = mmio_read_32(0xE00000D4); : mmio_write_32(0xE00000D8, 0); : mmio_write_32(0xE00000D4, tmp | 0x40010); : mmio_write_32(0xE00000D0, 0x110204F0);
Port 0x02, Offset 0x04 = TUNIT_MISC_CTL
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 276: mmio_read_32(0xE00F8044)
Another PCI operation! […]
Done
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/refc... PS1, Line 276: 0xB0
R_PCH_PMC_MTPMC1
Done
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 13:
(18 comments)
https://review.coreboot.org/c/coreboot/+/43133/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43133/4//COMMIT_MSG@10 PS4, Line 10: What should be done with all the magic numbers?
They aren't magic if they appear on document #538136 (atom e3800 datasheet) 😄
Done
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/Kcon... File src/soc/intel/baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/Kcon... PS4, Line 137: "Disable native high-speed PHY init"
Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/iosf.h:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 97:
align with tabs?
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 114: 0xa3
0xa6
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy_table.h:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 17: reva
a0
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/incl... PS5, Line 18: revb
b0
Done
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/modp... File src/soc/intel/baytrail/modphy_table.c:
PS3:
The first column is the IOSF-SB port (8-bit value), the second value is the offset (not sure of its […]
Done
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/3/src/soc/intel/baytrail/refc... PS3, Line 8: static u8 mmio_read_8(u32 addr) : { : return *(u8 *) addr; : } : : static u32 mmio_read_32(u32 addr) : { : return *(u32 *) addr; : } : : static void mmio_write_32(u32 addr, u32 val) : { : *(u32 *) addr = val; : } : : static void mmio_or_32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, tmp | val); : } : : static void mmio_and_32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, tmp & val); : } : : static void mmio_andor_32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = mmio_read_32(addr); : mmio_write_32(addr, (tmp & val1) | val2); : } :
Please use `#include <device/mmio.h>` instead. It also draws in <arch/mmio.h> […]
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 13: static u32 mmio_read32(u32 addr) : { : return *(u32 *) addr; : } : : static void mmio_write32(u32 addr, u32 val) : { : *(u32 *) addr = val; : } : : static void mmio_or32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, tmp | val); : } : : static void mmio_and32(u32 addr, u32 val) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, tmp & val); : } : : static void mmio_andor32(u32 addr, u32 val1, u32 val2) : { : u32 tmp; : : tmp = mmio_read32(addr); : mmio_write32(addr, (tmp & val1) | val2); : }
please use arch/mmio. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 47: #define IOSF_READ(op_read, port) \
Please fix this, it can bite you
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 64: static inline u64 rdtsc64(void) : { : struct tsc_struct tscval; : : tscval = rdtsc(); : return (u64) tscval.hi << 32 | (u64) tscval.lo; : } : : static void udelay(u64 usecs) : { : u64 needed_ticks, start_ticks; : : needed_ticks = usecs * tsc_freq_mhz(); : start_ticks = rdtsc64(); : while (start_ticks - rdtsc64() < needed_ticks) : ; : }
Please use delay. […]
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 84: 1
This will make more sense if you use shifts: […]
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 85: 4
(1 << 2)
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 86: 0xFFFFFFFD
~(1 << 1)
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 87: 0xFFFFFFF8
~(1 << 3)
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 114: iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F);
How about adding and-or functions?
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 137: Replacment
Replacement
Done
https://review.coreboot.org/c/coreboot/+/43133/5/src/soc/intel/baytrail/refc... PS5, Line 144: printk(BIOS_DEBUG, "refcode entry\n");
Given that this is coreboot and not the refcode, you might want a different message?
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#14).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 754 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/14
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 15:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... File src/soc/intel/baytrail/include/soc/modphy.h:
https://review.coreboot.org/c/coreboot/+/43133/1/src/soc/intel/baytrail/incl... PS1, Line 566: #define BAYTRAIL_MODPHY_REVB_OFFSET 0
I'd split the very large array in smaller arrays instead
Done
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... PS4, Line 140: |
&
Done
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/refc... PS4, Line 147: |
&
Done
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/10/src/soc/intel/baytrail/ref... PS10, Line 118: printk(BIOS_DEBUG, "ModPHY init entry\n");
It’d be great if you also added timestamps for running the ref code.
I am not sure how those work in coreboot.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#16).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 756 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/16
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... File src/soc/intel/baytrail/modphy_table.c:
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... PS4, Line 206: 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, : 0x00000043, 0x00004100, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004200, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007,
These entries are for B0 or later, and are the workaround for USB-related problems, sightings #43769 […]
Done
https://review.coreboot.org/c/coreboot/+/43133/4/src/soc/intel/baytrail/modp... PS4, Line 547: 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, : 0x00000043, 0x00004100, 0xfff00000, 0x0004fa01, 0x00000006, 0x00000007, : 0x00000043, 0x00004200, 0xfff00000, 0x0004ea01, 0x00000006, 0x00000007, : 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, : 0x00000043, 0x00004122, 0x00000000, 0x00004011, 0x00000006, 0x00000007, : 0x00000043, 0x00004222, 0x00000000, 0x06004015, 0x00000006, 0x00000007, : 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, : 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007,
These entries are for A0 only, and are the workaround for USB-related problems, sightings #4376904, […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 17: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... File src/soc/intel/baytrail/modphy_table.c:
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... PS17, Line 7: 0x000000a6 Port values are u8, drop the leading zeroes?
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... PS17, Line 7: 0x00000000, 0x00000001 Same story for read and write opcodes
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/ref... PS17, Line 40: (char *) (char *) Duplicate casts?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#18).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 756 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/18
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... File src/soc/intel/baytrail/modphy_table.c:
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... PS17, Line 7: 0x000000a6
Port values are u8, drop the leading zeroes?
Done
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/mod... PS17, Line 7: 0x00000000, 0x00000001
Same story for read and write opcodes
Done
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/ref... File src/soc/intel/baytrail/refcode_native.c:
https://review.coreboot.org/c/coreboot/+/43133/17/src/soc/intel/baytrail/ref... PS17, Line 40: (char *) (char *)
Duplicate casts?
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 18: Code-Review+2
Tested on Asrock Q1900M, it is able to boot.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43133
to look at the new patch set (#19).
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 756 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/19
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
Patch Set 19: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43133 )
Change subject: soc/intel/baytrail: Add native refcode replacement ......................................................................
soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I91977c509022b0078804dc151d27296260e24bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/include/soc/iosf.h A src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/iosf.c A src/soc/intel/baytrail/modphy_table.c A src/soc/intel/baytrail/refcode_native.c 8 files changed, 756 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a436e24..b23f56d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -133,13 +133,15 @@
config HAVE_REFCODE_BLOB depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." + bool "Use a binary refcode blob instead of native ModPHY init" default n help - The reference code blob will be placed into cbfs. + Use the ChromeBook refcode to intitialize high-speed PHYs instead of + native code.
if HAVE_REFCODE_BLOB
+# Ask for the blob if the user wants it config REFCODE_BLOB_FILE string "Path and filename to reference code blob." default "refcode.elf" diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 451f29e..bfa1846 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -49,7 +49,12 @@ ramstage-y += southcluster.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c + +ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) +ramstage-y += refcode.c +else +ramstage-y += modphy_table.c refcode_native.c +endif
smm-y += iosf.c smm-y += pmutil.c diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 15d77de..d4fcdf3 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -9,34 +9,33 @@ /* * The Bay Trail SoC has a message network called IOSF Sideband. The access * routines are through 3 registers in PCI config space of 00:00.0: - * MCR - control register - * MDR - data register + * MCR - control register + * MDR - data register * MCRX - control register extension * The extension register is only used for addresses that don't fit * into the 8 bit register address. */
-#ifndef PCI_DEV -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) -#endif #define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC)
-#define MCR_REG 0xd0 -#define IOSF_OPCODE(x) ((x) << 24) -#define IOSF_PORT(x) ((0xff & (x)) << 16) -#define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_REG_UPPER(x) (((~0xff) & (x))) -#define IOSF_BYTE_EN_0 0x10 -#define IOSF_BYTE_EN_1 0x20 -#define IOSF_BYTE_EN_2 0x40 -#define IOSF_BYTE_EN_3 0x80 -#define IOSF_BYTE_EN \ - (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) -#define MDR_REG 0xd4 -#define MCRX_REG 0xd8 +#define IOSF_OPCODE(x) ((x) << 24) +#define IOSF_PORT(x) ((0xff & (x)) << 16) +#define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) ((~0xff) & (x)) + +#define IOSF_BYTE_EN_0 0x10 +#define IOSF_BYTE_EN_1 0x20 +#define IOSF_BYTE_EN_2 0x40 +#define IOSF_BYTE_EN_3 0x80 +#define IOSF_BYTE_EN \ + (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) + +#define MCR_REG 0xd0 +#define MDR_REG 0xd4 +#define MCRX_REG 0xd8 + +uint32_t iosf_read_port(uint32_t cr, int reg); +void iosf_write_port(uint32_t cr, int reg, uint32_t val);
uint32_t iosf_aunit_read(int reg); void iosf_aunit_write(int reg, uint32_t val); @@ -49,6 +48,8 @@ /* Some registers are per channel while the globals live in dunit 0 */ uint32_t iosf_dunit_ch0_read(int reg); uint32_t iosf_dunit_ch1_read(int reg); +uint32_t iosf_cunit_read(int reg); +void iosf_cunit_write(int reg, uint32_t val); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); uint32_t iosf_usbphy_read(int reg); @@ -87,12 +88,13 @@ /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ #define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ +#define IOSF_PORT_CUNIT 0x08 #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SEC 0x44 /* SEC */ @@ -109,7 +111,7 @@ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_PCIEPHY 0xa6 /* PCIE PHY */ #define IOSF_PORT_SSUS 0xa8 /* SUS */ #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */
@@ -122,6 +124,8 @@ #define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) #define IOSF_OP_READ_BUNIT 0x10 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) +#define IOSF_OP_READ_CUNIT 0x10 +#define IOSF_OP_WRITE_CUNIT (IOSF_OP_READ_CUNIT | 1) #define IOSF_OP_READ_PMC 0x06 #define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) #define IOSF_OP_READ_GFX 0x00 diff --git a/src/soc/intel/baytrail/include/soc/modphy_table.h b/src/soc/intel/baytrail/include/soc/modphy_table.h new file mode 100644 index 0000000..9a483c4 --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/modphy_table.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BAYTRAIL_MODPHY_TABLE_H_ +#define _BAYTRAIL_MODPHY_TABLE_H_ + +struct modphy_entry { + u8 port; + u32 reg; + u32 mask; + u32 value; + u8 op_read; + u8 op_write; +}; + +#define MODPHY_ENTRY_END ((struct modphy_entry) { 0, 0, 0, 0, 0, 0 }) + +extern struct modphy_entry reva0_modphy_table[]; /* SOC stepping A0/A1 */ +extern struct modphy_entry revb0_modphy_table[]; /* SOC stepping B0 or later */ + +#endif diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 8f30331..51189cf 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -11,11 +11,9 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); -#if CONFIG(HAVE_REFCODE_BLOB) +/* The baytrail_run_reference_code() function is provided by either + * native refcode or the ChromeBook refcode wrapper */ void baytrail_run_reference_code(void); -#else -static inline void baytrail_run_reference_code(void) {} -#endif void baytrail_init_scc(void); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 5a83310..21060ee 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -15,7 +15,7 @@ }
/* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) +uint32_t iosf_read_port(uint32_t cr, int reg) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); @@ -23,7 +23,7 @@ return read_iosf_reg(MDR_REG); }
-static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +void iosf_write_port(uint32_t cr, int reg, uint32_t val) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); @@ -68,6 +68,16 @@ iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); }
+uint32_t iosf_cunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(CUNIT), reg); +} + +void iosf_cunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(CUNIT), reg, val); +} + uint32_t iosf_punit_read(int reg) { return iosf_read_port(IOSF_READ(PMC), reg); diff --git a/src/soc/intel/baytrail/modphy_table.c b/src/soc/intel/baytrail/modphy_table.c new file mode 100644 index 0000000..f028c8f --- /dev/null +++ b/src/soc/intel/baytrail/modphy_table.c @@ -0,0 +1,569 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <soc/modphy_table.h> + +struct modphy_entry reva0_modphy_table[] = { /* SOC stepping A0/A1 */ + { 0xa6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa3, 0x00002208, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002408, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002238, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x00002438, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x000080a4, 0xffff0000, 0x0000f487, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008100, 0xfffffffc, 0x00000003, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002318, 0x0000ffff, 0x45140000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0x80ffffff, 0x02000000, 0x00, 0x01 }, + { 0xa3, 0x00002304, 0xff80ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + { 0xa3, 0x00002518, 0x0000ffff, 0x47140000, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0x80ffffff, 0x04000000, 0x00, 0x01 }, + { 0xa3, 0x00002504, 0xff80ffff, 0x00040000, 0x00, 0x01 }, + { 0xa3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + /* Workaround for #4376904, #4682850, #4753319 */ + { 0x43, 0x00007f04, 0xffff0000, 0x00004700, 0x06, 0x07 }, + { 0x43, 0x00004100, 0xfff00000, 0x0004fa01, 0x06, 0x07 }, + { 0x43, 0x00004200, 0xfff00000, 0x0004ea01, 0x06, 0x07 }, + { 0x43, 0x00004300, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004400, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004122, 0x00000000, 0x00004011, 0x06, 0x07 }, + { 0x43, 0x00004222, 0x00000000, 0x06004015, 0x06, 0x07 }, + { 0x43, 0x00004500, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004600, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004700, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004800, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + MODPHY_ENTRY_END +}; + +struct modphy_entry revb0_modphy_table[] = { /* SOC stepping B0 or later */ + { 0xa6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa3, 0x00002208, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002408, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002238, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x00002438, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x000080a4, 0xffff0000, 0x0000f487, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008100, 0xfffffffc, 0x00000003, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002318, 0x0000ffff, 0x45140000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0x80ffffff, 0x02000000, 0x00, 0x01 }, + { 0xa3, 0x00002304, 0xff80ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + { 0xa3, 0x00002518, 0x0000ffff, 0x47140000, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0x80ffffff, 0x04000000, 0x00, 0x01 }, + { 0xa3, 0x00002504, 0xff80ffff, 0x00040000, 0x00, 0x01 }, + { 0xa3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + /* Workaround for #4376904, #4682850, #4753319 */ + { 0x43, 0x00007f04, 0xffff0000, 0x00004700, 0x06, 0x07 }, + { 0x43, 0x00004100, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004200, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004300, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004400, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004500, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004600, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004700, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004800, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0xa3, 0x00008100, 0xfffffcff, 0x00000300, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x85850000, 0x00, 0x01 }, + { 0xa3, 0x00002290, 0x00ffffff, 0x00600000, 0x00, 0x01 }, + { 0xa3, 0x00002490, 0x00ffffff, 0x00600000, 0x00, 0x01 }, + { 0xa3, 0x0000230c, 0xff00ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000250c, 0xff00ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x000080d0, 0xffffff0f, 0x00000050, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x0000030c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000030c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000318, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000318, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000050c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000050c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000518, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000518, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000070c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000070c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000718, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000718, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000090c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000090c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000918, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000918, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + MODPHY_ENTRY_END +}; diff --git a/src/soc/intel/baytrail/refcode_native.c b/src/soc/intel/baytrail/refcode_native.c new file mode 100644 index 0000000..a9976fb --- /dev/null +++ b/src/soc/intel/baytrail/refcode_native.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> +#include <cpu/x86/tsc.h> +#include <device/pci.h> +#include <delay.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> +#include <soc/iosf.h> +#include <soc/iomap.h> +#include <soc/ramstage.h> +#include <soc/modphy_table.h> + +#define IOSF_READ(op_read, port) \ + (IOSF_OPCODE(op_read) | IOSF_PORT(port)) +#define IOSF_WRITE(op_write, port) \ + (IOSF_OPCODE(op_write) | IOSF_PORT(port)) + +static void program_modphy_table(struct modphy_entry *table) +{ + u32 tmp; + + for (; table->port; ++table) { + tmp = iosf_read_port(IOSF_READ(table->op_read, table->port), table->reg); + iosf_write_port(IOSF_WRITE(table->op_write, table->port), table->reg, + (tmp & table->mask) | table->value); + } +} + +static void gpio_sc_sdcard_workaround(void) +{ + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *) IO_BASE_ADDRESS + 0x690, (1 << 3)); + udelay(100); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + udelay(100); + write32((char *) IO_BASE_ADDRESS + 0x830, 0x78480); + udelay(40); + write32((char *) IO_BASE_ADDRESS + 0x830, 0x78080); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + udelay(100); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrsetbits32((char *) IO_BASE_ADDRESS + 0x690, 7, (1 << 0)); +} + +#define BUNIT_BALIMIT0 0x0b +#define AUNIT_AVCCTL 0x21 +#define AUNIT_ACFCACV 0x60 +#define CUNIT_ACCESS_CTRL_VIOL 0x41 +#define CUINT_SSA_REGIONAL_TRUNKGATE_CTL 0x43 +#define TUNIT_CTL 0x03 +#define TUNIT_MISC_CTL 0x04 + +static void ssa_safe_config(void) +{ + u32 tmp; + + tmp = iosf_bunit_read(BUNIT_BALIMIT0); + iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); + + tmp = iosf_aunit_read(AUNIT_AVCCTL); + iosf_aunit_write(AUNIT_AVCCTL, tmp | 0x80000100); + + tmp = iosf_aunit_read(AUNIT_ACFCACV); + iosf_aunit_write(AUNIT_ACFCACV, tmp & 0x7FFFFFFF); + + tmp = iosf_cunit_read(CUNIT_ACCESS_CTRL_VIOL); + iosf_cunit_write(CUNIT_ACCESS_CTRL_VIOL, tmp & 0x7FFFFFFF); + + iosf_cunit_write(CUINT_SSA_REGIONAL_TRUNKGATE_CTL, 0x70008); + + tmp = iosf_cpu_bus_read(TUNIT_CTL); + iosf_cpu_bus_write(TUNIT_CTL, tmp | 0x110430); + + tmp = iosf_cpu_bus_read(TUNIT_MISC_CTL); + iosf_cpu_bus_write(TUNIT_MISC_CTL, tmp | 0x40010); +} + +#define R_PCH_PMC_MTPMC1 0xb0 + +/* + * Replacement for refcode.elf + */ +void baytrail_run_reference_code(void) +{ + u32 tmp; + size_t pollcnt; + + printk(BIOS_DEBUG, "ModPHY init entry\n"); + + if (pci_read_config8(pcidev_on_root(LPC_DEV, LPC_FUNC), REVID) < RID_B_STEPPING_START) { + printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n"); + program_modphy_table(reva0_modphy_table); + } else { + printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n"); + program_modphy_table(revb0_modphy_table); + } + + setbits32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8); + + for (pollcnt = 0; pollcnt < 10; ++pollcnt) { + tmp = read32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1); + printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp); + if (!(tmp & 8)) + break; + } + + gpio_sc_sdcard_workaround(); + ssa_safe_config(); + + printk(BIOS_DEBUG, "ModPHY init done\n"); +}
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