Change in coreboot[master]: southbridge/broadcom: Remove spaces before/after parenthesis

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25875

Change subject: southbridge/broadcom: Remove spaces before/after parenthesis
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southbridge/broadcom: Remove spaces before/after parenthesis

Change-Id: Ic43b5ddaa395658ab7c34cdd004516884a20b005
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/broadcom/bcm5785/bcm5785.c
M src/southbridge/broadcom/bcm5785/early_setup.c
M src/southbridge/broadcom/bcm5785/sata.c
M src/southbridge/broadcom/bcm5785/sb_pci_main.c
M src/southbridge/broadcom/bcm5785/smbus.h
5 files changed, 14 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/25875/1

diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index d9a1268..2ce00a7 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -29,14 +29,14 @@
    /* See if we are on the behind the pcix bridge */
    bus_dev = dev->bus->dev;
    if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
-		(bus_dev->device == 0x0036 )) // device under PCI-X Bridge
+		(bus_dev->device == 0x0036)) // device under PCI-X Bridge
    {
    	unsigned devfn;
    	devfn = bus_dev->path.pci.devfn + (1 << 3);
    	sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
    	// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
    } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
-		(bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+		(bus_dev->device == 0x0104)) // device under PCI Bridge(under PCI-X)
    {
    	unsigned devfn;
    	devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
@@ -46,7 +46,7 @@
    else { // same bus
    	unsigned devfn;
    	devfn = (dev->path.pci.devfn) & ~7;
-		if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) {
    		if (dev->device == 0x0036) //PCI-X Bridge
    		{ devfn += (1<<3); }
    		else if (dev->device == 0x0223) // USB
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 7235444..849f0a4 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -47,13 +47,13 @@

dword_old = pci_read_config32(dev, 0x4c);
    dword = dword_old | (1<<4); //enable Timer Func
-	if (dword != dword_old ) {
+	if (dword != dword_old) {
    	pci_write_config32(dev, 0x4c, dword);
    }

dword_old = pci_read_config32(dev, 0x6c);
    dword = dword_old | (1<<9); //unhide Timer Func in pci space
-	if (dword != dword_old ) {
+	if (dword != dword_old) {
    	pci_write_config32(dev, 0x6c, dword);
    }

@@ -149,7 +149,7 @@
    // bit 1: enable upsteam messages
    // bit 0: enable shutdowm message to init generation
    dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
-	if (dword != dword_old ) {
+	if (dword != dword_old) {
    	pci_write_config32(dev, 0x6c, dword);
    }
 }
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 02331d9..57df3d2 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -42,13 +42,13 @@

write32(mmio_base + 0x10f0, 0x40000001);
    	write32(mmio_base + 0x8c, 0x00ff2007);
-		mdelay( 10 );
+		mdelay(10);
    	write32(mmio_base + 0x8c, 0x78592009);
-		mdelay( 10 );
+		mdelay(10);
    	write32(mmio_base + 0x8c, 0x00082004);
-		mdelay( 10 );
+		mdelay(10);
    	write32(mmio_base + 0x8c, 0x00002004);
-		mdelay( 10 );
+		mdelay(10);

//init PHY

diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index ab0cd05..c129434 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -43,9 +43,9 @@
    if (nmi_option) {
    	byte &= ~(1 << 7); /* set NMI */
    } else {
-		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+		byte |= (1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
    }
-	if ( byte != byte_old) {
+	if (byte != byte_old) {
    	outb(byte, 0x70);
    }

diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index 8ebe203..1c3c9d7 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -66,10 +66,10 @@

val = inb(smbus_io_base + SMBHSTSTAT);
    	val &= 0x1f; // mask off reserved bits
-		if ( val & 0x1c) {
+		if (val & 0x1c) {
    		return -5; // error
    	}
-		if ( val == 0x02) {
+		if (val == 0x02) {
    		outb(val, smbus_io_base + SMBHSTSTAT); // clear status
    		return 0; //
    	}