Attention is currently required from: Duncan Laurie, Kyösti Mälkki. Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Tim Wawrzynczak, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52723
to look at the new patch set (#2).
Change subject: drivers/i2c/designware: Use safe defaults for SCL parameters ......................................................................
drivers/i2c/designware: Use safe defaults for SCL parameters
Inspired by discussion in CB:22822.
If I2C bus step response has not been measured, assume the layout to have been designed with a minimal capacitance and SCL rise and fall times of 0 ns. The calculations will add the required amount of reference clocks for the host to drive SCL high or low, such that the maximum bus frequency specification is met.
Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 2 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/52723/2