Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55070 )
Change subject: [NOTFORMERGE]link Agesa into bootblock ......................................................................
[NOTFORMERGE]link Agesa into bootblock
Untested but it does seem to build for AGESA targets.
For AGESA targets the APs are started by the BSP in romstage and need to jump past the bootblock into the romstage. When there is a separate romstage this is complicated as the APs in boot need to know where to jump in romstage. This is done by setting a pointer in BIOSRAM.
When the romstage is linked inside the bootblock there is no need for such tricks as the symbol for the AP jump address can directly be referenced.
Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/Kconfig M src/arch/x86/bootblock.ld M src/arch/x86/car.ld M src/cpu/amd/agesa/Kconfig M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/vendorcode/amd/agesa/Makefile.inc 8 files changed, 28 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55070/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a488b55..4e7d799 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -189,7 +189,7 @@
config C_ENV_BOOTBLOCK_SIZE hex - default 0x40000 if !FIXED_BOOTBLOCK_SIZE + default 0x100000 if !FIXED_BOOTBLOCK_SIZE help This is only the default maximum of bootblock size for linking purposes. Platforms may provide different limit and need to diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 3cd0900..b66f1cc 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -22,6 +22,11 @@
_bootblock = .;
+.data . : { + *(.data); + *(.data.*); +} + INCLUDE "bootblock/lib/program.ld"
/* @@ -29,7 +34,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ - PROGRAM_SZ = SIZEOF(.text) + 512; + PROGRAM_SZ = SIZEOF(.text) + 512 + SIZEOF(.data);
. = MIN(_ID_SECTION, _FIT_POINTER) - EARLYASM_SZ; . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5a46b8b..39c9305 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -115,8 +115,8 @@
. = 0xffffff00; .illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/bootblock*/buildOpts.o" "*/bootblock*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/bootblock*/buildOpts.o" "*/bootblock*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) }
_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 51b61a1..7ce80fb 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -47,7 +47,7 @@
config S3_DATA_POS hex - default 0xFFFF0000 + default 0xFFF00000
config S3_DATA_SIZE int diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index df9876a..c8e4330 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -8,6 +8,7 @@ #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/agesa_helper.h>
#define EARLY_VMTRR_FLASH 6
@@ -42,7 +43,13 @@ if (CONFIG(UDELAY_LAPIC)) enable_lapic();
- void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); - ap_romstage_entry(); /* execution does not return */ + if (CONFIG(SEPARATE_ROMSTAGE)) { + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); + ap_romstage_entry(); /* execution does not return */ + } else { + /* We can just call that function directly as romstage symbols + are in the bootblock */ + ap_romstage_main(); + } halt(); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 6255970..f00aaab 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,11 +27,6 @@ agesa_set_interface(cb); }
-/* APs will enter directly here from bootblock, bypassing verstage - * and potential fallback / normal bootflow detection. - */ -static void ap_romstage_main(void); - void romstage_main(void) { struct postcar_frame pcf; @@ -79,7 +74,10 @@ /* We do not return. */ }
-static void ap_romstage_main(void) +/* APs will enter directly here from bootblock, bypassing verstage + * and potential fallback / normal bootflow detection. + */ +void ap_romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 120e74a..08ca68e 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -42,4 +42,6 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void);
+void ap_romstage_main(void); + #endif /* _AGESA_HELPER_H_ */ diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..68d9b8c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -27,13 +27,16 @@ @printf " AGESA $(subst $(obj)/,,$(@))\n" $(AR_libagesa) rcsDT $@ $+
+bootblock-libs += $(obj)/libagesa.a romstage-libs += $(obj)/libagesa.a ramstage-libs += $(obj)/libagesa.a
# buildOpts should be in libagesa +$(obj)/bootblock/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) $(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) $(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
+$(obj)/bootblock/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) $(obj)/romstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) $(obj)/ramstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
-
Arthur Heymans (Code Review)