Change in coreboot[master]: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/graphics.c
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40841/1

diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index c240f3b..2af4cc4 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -42,22 +42,21 @@
 static void soc_config_pwrmbase(void)
 {
    uint32_t reg32;
+	uint16_t reg16;

/*
     * Assign Resources to PWRMBASE
     * Clear BIT 1-2  Command Register
     */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);

/* Program PWRM Base */
    pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);

/* Enable Bus Master and MMIO Space */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MEMORY;
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);

/* Enable PWRM in PMC */
    reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index b8192c9..a1ec5bb 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -43,9 +43,9 @@
    	return;

/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config16(dev, PCI_COMMAND, reg16);

/* Initialize PCI device, load/execute BIOS Option ROM */
    pci_dev_init(dev);

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40841

to look at the new patch set (#2).

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/graphics.c
2 files changed, 7 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40841/2

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40841

to look at the new patch set (#3).

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/graphics.c
2 files changed, 7 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40841/3

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3: Code-Review+1

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix 
"Fix" resembles some issue exist and hence this CL has introduced, is there any real issue behind this modification or just optimization ?

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix
> "Fix" resembles some issue exist and hence this CL has introduced, is there any real issue behind th […]

Thank you for the review.
This is only an optimization as this register is a 16-bit.

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix
> Thank you for the review. […]

There is a theoretical issue. The register is 16 bits wide. Using a 32-bit
read-modify-write can accidentally clear status bits in the adjacent register.

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix
> There is a theoretical issue. The register is 16 bits wide. Using a 32-bit […]

PMC status register is mostly RO hence this is really "theoretical" 😊

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix
> PMC status register is mostly RO hence this is really "theoretical" 😊

Are the answers ok?
can we move to "resolved" status?
Thank you.

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix
> Are the answers ok? […]

Done

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40841

to look at the new patch set (#4).

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/icelake/bootblock/pch.c
1 file changed, 5 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40841/4

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 5: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/icelake/bootblock/pch.c
1 file changed, 5 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 402fb9a..6ebf910 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -41,22 +41,21 @@
 static void soc_config_pwrmbase(void)
 {
    uint32_t reg32;
+	uint16_t reg16;

/*
     * Assign Resources to PWRMBASE
     * Clear BIT 1-2  Command Register
     */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);

/* Program PWRM Base */
    pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);

/* Enable Bus Master and MMIO Space */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MEMORY;
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);

/* Enable PWRM in PMC */
    reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 7:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4791
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4790
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4789
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4788

Please note: This test is under development and might not be accurate at all!