[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Default to X2APIC support

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74184 )

Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support
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soc/intel/xeon_sp/spr: Default to X2APIC support

When more than 255 CPU cores are present on a board
the X2APIC must be used.

Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.

Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 7aa1fec..832aab5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -8,6 +8,7 @@
    select SAVE_MRC_AFTER_FSPS
    select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
    select DISABLE_ACPI_HIBERNATE
+	select DEFAULT_X2APIC_RUNTIME

config CHIPSET_DEVICETREE
    string