[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Ravishankar Sarawadi (Code Review)]

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel.

Hello Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Utkarsh H Patel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78163?usp=email

to look at the new patch set (#6).

The following approvals got outdated and were removed:
Code-Review+1 by Cliff Huang, Code-Review+1 by Eric Lai, Code-Review+1 by Jamie Ryu, Verified+1 by build bot (Jenkins)

Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
......................................................................

soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

Within TBT PCIe, following register offsets have been updated for
production silicon. Update ASL with new offsets.
1. MPC - Miscellaneous Port Configuration Register
2. RPPGEN - Root Port Power Gating Enable
3. SMSCS - SMI/SCI Status Register

TEST= Check TBT PCIe Tunnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi 
---
M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
1 file changed, 24 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/6