Change in coreboot[master]: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST - coreboot-gerrit

3 Aug 2020


      Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 )
Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
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Patch Set 2:
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Patch Set 2: -Code-Review
Thinking about this, MP init works different with FSP2.1, so it
should be tested, IMHO. Might even be a no-op.
SkipMpInit was moved to FSP-M; Analysis of the most recent icl Fsp showed that the same applies to icl as does for skl or cnl in regard to LT_MEMORY_LOCK -> the patch is required, when SkipMpInitPreMem=1.
Could anyone test this please?
Without this patch and native mp init, msr 0x2e7 should be 0x0.
With this patch applied 0x2e7 should be 0x1.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib728e61bc874acf505348e72c00a99e0a6efd2cb
Gerrit-Change-Number: 36357
Gerrit-PatchSet: 2
Gerrit-Owner: Michael Niewöhner
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