Change in coreboot[master]: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44630 )

Change subject: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor
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[TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor

This is test patch to update PL1 and PL2 on halvor.

Signed-off-by: John Su 
Change-Id: I26be0031c70264cd652ceb288ade30dd4d0c7c92
---
M src/mainboard/google/volteer/variants/halvor/overridetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44630/1

diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index c6ac1b7..d85bc3e 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -17,7 +17,32 @@

register "SaGv" = "SaGv_Disabled"

+	register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 15,
+	}"
+
    device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+
+				register "controls.power_limits.pl1" = "{
+                                        .min_power = 3000,
+                                        .max_power = 7000,
+                                        .time_window_min = 1 * MSECS_PER_SEC,
+                                        .time_window_max = 1 * MSECS_PER_SEC,
+                                        .granularity = 200,}"
+
+                                register "controls.power_limits.pl2" = "{
+                                        .min_power = 7000,
+                                        .max_power = 15000,
+                                        .time_window_min = 1 * MSECS_PER_SEC,
+                                        .time_window_max = 1 * MSECS_PER_SEC,
+                                        .granularity = 1000,}"
+
+				device generic 0 on end
+			end
+		end # DPTF
    	device pci 15.0 on
    		chip drivers/i2c/generic
    			register "hid" = ""10EC5682""

[John Su (Code Review)]

John Su has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44630 )

Change subject: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor
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Abandoned