Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32286
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capicity is 32GB.
TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32286/1
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d95a4eb..c66eb0a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <console/console.h> #include <device/pci_ops.h> #include <cbmem.h> #include <device/device.h> @@ -21,6 +22,8 @@ #include <device/pci_ids.h> #include <intelblocks/acpi.h> #include <intelblocks/systemagent.h> +#include <smbios.h> +#include <memory_info.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> @@ -275,6 +278,37 @@ sa_add_imr_resources(dev, &index); }
+#if CONFIG(GENERATE_SMBIOS_TABLES) +static int sa_smbios_write_type_16(struct device *dev, int *handle, + unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len - 2; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + /* TBD, meminfo hob have information about ECC */ + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + /* no error information handle available */ + t->memory_error_information_handle = 0xFFFE; + t->maximum_capacity = 32 * (GiB / KiB); /* 32GB as default */ + t->number_of_memory_devices = meminfo->dimm_cnt; + + *current += len; + *handle += 1; + return len; +} +#endif + void enable_power_aware_intr(void) { uint8_t pair; @@ -295,6 +329,9 @@ #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = sa_smbios_write_type_16, +#endif };
static const unsigned short systemagent_ids[] = {
Hello Patrick Rudolph, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32286
to look at the new patch set (#2).
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capicity is 32GB.
TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32286/2
Hello Patrick Rudolph, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32286
to look at the new patch set (#4).
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capicity is 32GB.
BUG=b:129485635 TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32286/4
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32286 )
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
Patch Set 4: Code-Review+1
Hello Patrick Rudolph, Subrata Banik, Patrick Rudolph, Duncan Laurie, hannah.williams@dell.com, Bora Guvendik, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32286
to look at the new patch set (#5).
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capacity is 32GB.
BUG=b:129485635 TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32286/5
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32286 )
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
Patch Set 5: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32286 )
Change subject: soc/intel/common: Inject SMBIOS type 16 table ......................................................................
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capacity is 32GB.
BUG=b:129485635 TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32286 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 35 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d95a4eb..0f91156 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <intelblocks/acpi.h> #include <intelblocks/systemagent.h> +#include <smbios.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> @@ -275,6 +276,37 @@ sa_add_imr_resources(dev, &index); }
+#if CONFIG(GENERATE_SMBIOS_TABLES) +static int sa_smbios_write_type_16(struct device *dev, int *handle, + unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len - 2; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + /* TBD, meminfo hob have information about ECC */ + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + /* no error information handle available */ + t->memory_error_information_handle = 0xFFFE; + t->maximum_capacity = 32 * (GiB / KiB); /* 32GB as default */ + t->number_of_memory_devices = meminfo->dimm_cnt; + + *current += len; + *handle += 1; + return len; +} +#endif + void enable_power_aware_intr(void) { uint8_t pair; @@ -295,6 +327,9 @@ #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = sa_smbios_write_type_16, +#endif };
static const unsigned short systemagent_ids[] = {
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Duncan Laurie (Code Review) -
Lijian Zhao (Code Review)
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Patrick Rudolph (Code Review)