[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()

[SH Kim (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim.

Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81436?usp=email

to look at the new patch set (#4).

Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................

mb/google/{brya,hades}: use soc index for variant_update_power_limits()

The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.

I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c :
const struct cpu_power_limits limits[] = {
    {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}

And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this CL: msr_pl4 was not chaged, it's always 114
- After this CL: msr_pl4 was changed to 80

BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.

Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
2 files changed, 64 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81436/4