Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47744 )
Change subject: nb/intel/sandybridge: Increase tRWDRDD with fast RAM ......................................................................
nb/intel/sandybridge: Increase tRWDRDD with fast RAM
This has been reported to increase stability, and vendor BIOS also does the same.
Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47744/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7e93786..6ba91c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2778,6 +2778,9 @@
void set_read_write_timings(ramctr_timing *ctrl) { + /* Use a larger delay when running fast to improve stability */ + const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; + int channel, slotrank;
FOR_ALL_POPULATED_CHANNELS { @@ -2800,7 +2803,7 @@ .tRRDD = val, .tWWDR = val, .tWWDD = val, - .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, .tWRDRDD = tWRDRDD, .tRWSR = 2, .dec_wrd = 1,
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47744 )
Change subject: nb/intel/sandybridge: Increase tRWDRDD with fast RAM ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47744 )
Change subject: nb/intel/sandybridge: Increase tRWDRDD with fast RAM ......................................................................
nb/intel/sandybridge: Increase tRWDRDD with fast RAM
This has been reported to increase stability, and vendor BIOS also does the same.
Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7e93786..6ba91c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2778,6 +2778,9 @@
void set_read_write_timings(ramctr_timing *ctrl) { + /* Use a larger delay when running fast to improve stability */ + const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; + int channel, slotrank;
FOR_ALL_POPULATED_CHANNELS { @@ -2800,7 +2803,7 @@ .tRRDD = val, .tWWDR = val, .tWWDD = val, - .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, .tWRDRDD = tWRDRDD, .tRWSR = 2, .dec_wrd = 1,
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Georgi (Code Review)