[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74844 )

Change subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
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soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte

The memory map granularity for those devices is 4kByte.

Signed-off-by: Felix Held 
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/74844/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index b8fb923..5b836ea 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -121,7 +121,7 @@
    	   FLASH_BELOW_4GB_MAPPING_REGION_SIZE);

/* Add a memory resource for the SPI BAR. */
-	mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
+	mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);

res = new_resource(dev, 3); /* IOAPIC */
    res->base = IO_APIC_ADDR;