[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave

[Raymond Chung (Code Review)]

Attention is currently required from: Raymond Chung, Tim Wawrzynczak, Zhuohao Lee.

Hello build bot (Jenkins), Derek Huang, Tim Wawrzynczak, Zhuohao Lee,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68806

to look at the new patch set (#6).

Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
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mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave

The brask DDR4 is set to interleave, due to the limited number of
gaelin PCB layers and the traces need to be smooth,
we will use non-interleave for gaelin DDR4.

BUG=b:255399229, b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and pass MRC memory training

Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Signed-off-by: Raymond Chung 
---
A src/mainboard/google/brya/variants/gaelin/Makefile.inc
A src/mainboard/google/brya/variants/gaelin/memory.c
2 files changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68806/6