Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 37: INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), BTW, I think the kernel has a bug: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
It cannot skip these 9 reserved GPIOs when numbering the pads in community 0. That will cause it to calculate the DW0-2 config register offsets incorrectly for the pads after this in the community. I think if you try to make the kernel configure any of the DW registers for a pad in GPP_A/S/R, you will see that it is writing to the wrong offset. Can you please follow up on this? If the experiment proves that the behavior is wrong, this will have to be fixed in the kernel as well.
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Furquan Shaikh (Code Review)