Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34704 )
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/Makefile.inc R src/cpu/x86/smm/stage_cache.c M src/drivers/intel/fsp1_1/Makefile.inc M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 7 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34704/1
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 5c7aab3..fe149f1 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,6 +42,10 @@
ifeq ($(CONFIG_SMM_TSEG),y)
+ramstage-y += stage_cache.c +romstage-y += stage_cache.c +postcar-y += stage_cache.c + smmstub-y += smm_stub.S
smm-y += smm_module_handler.c diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/cpu/x86/smm/stage_cache.c similarity index 84% rename from src/drivers/intel/fsp1_1/stage_cache.c rename to src/cpu/x86/smm/stage_cache.c index ab0c1c0..56581ad 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/cpu/x86/smm/stage_cache.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +16,9 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <stage_cache.h> +#include <types.h>
-void stage_cache_external_region(void **base, size_t *size) +void __weak stage_cache_external_region(void **base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9..1372e98 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c
ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c @@ -37,13 +36,11 @@ ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-y += stage_cache.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
-postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c postcar-y += exit_car.S diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 4ff4252..2a0f33d 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -82,15 +82,6 @@ return CONFIG_SMM_TSEG_SIZE; }
-void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 4ff4252..2a0f33d 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -82,15 +82,6 @@ return CONFIG_SMM_TSEG_SIZE; }
-void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 489462d..12c057b 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -22,18 +22,6 @@ #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> #include <soc/pm.h> -#include <stage_cache.h> - -#if !CONFIG(PLATFORM_USES_FSP1_1) -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} -#endif
void smm_southbridge_clear_state(void) {
Hello Patrick Rudolph, Huang Jin, Lee Leahy, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34704
to look at the new patch set (#3).
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/Makefile.inc R src/cpu/x86/smm/stage_cache.c M src/drivers/intel/fsp1_1/Makefile.inc M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 12 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34704/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34704 )
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34704/3/src/cpu/x86/smm/stage_cache... File src/cpu/x86/smm/stage_cache.c:
https://review.coreboot.org/c/coreboot/+/34704/3/src/cpu/x86/smm/stage_cache... PS3, Line 22: { trailing whitespace
Hello Patrick Rudolph, Huang Jin, Lee Leahy, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34704
to look at the new patch set (#4).
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/Makefile.inc R src/cpu/x86/smm/stage_cache.c M src/drivers/intel/fsp1_1/Makefile.inc M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 12 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34704/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34704 )
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
Patch Set 4: Code-Review+2
Hello Patrick Rudolph, Huang Jin, Arthur Heymans, Lee Leahy, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34704
to look at the new patch set (#5).
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/smm/Makefile.inc R src/cpu/x86/smm/stage_cache.c M src/drivers/intel/fsp1_1/Makefile.inc M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 12 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34704/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34704 )
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34704 )
Change subject: arch/x86: Move TSEG_STAGE_CACHE implementation ......................................................................
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/cpu/x86/smm/Makefile.inc R src/cpu/x86/smm/stage_cache.c M src/drivers/intel/fsp1_1/Makefile.inc M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 12 insertions(+), 38 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 5c7aab3..fe149f1 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,6 +42,10 @@
ifeq ($(CONFIG_SMM_TSEG),y)
+ramstage-y += stage_cache.c +romstage-y += stage_cache.c +postcar-y += stage_cache.c + smmstub-y += smm_stub.S
smm-y += smm_module_handler.c diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/cpu/x86/smm/stage_cache.c similarity index 78% rename from src/drivers/intel/fsp1_1/stage_cache.c rename to src/cpu/x86/smm/stage_cache.c index ab0c1c0..7806290 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/cpu/x86/smm/stage_cache.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +16,14 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <stage_cache.h> +#include <types.h>
-void stage_cache_external_region(void **base, size_t *size) +int __weak smm_subregion(int sub, void **base, size_t *size) +{ + return -1; +} + +void __weak stage_cache_external_region(void **base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9..1372e98 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c
ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c @@ -37,13 +36,11 @@ ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-y += stage_cache.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
-postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c postcar-y += exit_car.S diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 4ff4252..f0051e4 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -23,7 +23,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> -#include <stage_cache.h> #include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/iomap.h> @@ -82,15 +81,6 @@ return CONFIG_SMM_TSEG_SIZE; }
-void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 4ff4252..f0051e4 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -23,7 +23,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> -#include <stage_cache.h> #include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/iomap.h> @@ -82,15 +81,6 @@ return CONFIG_SMM_TSEG_SIZE; }
-void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 489462d..12c057b 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -22,18 +22,6 @@ #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> #include <soc/pm.h> -#include <stage_cache.h> - -#if !CONFIG(PLATFORM_USES_FSP1_1) -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} -#endif
void smm_southbridge_clear_state(void) {
-
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build bot (Jenkins) (Code Review)
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Furquan Shaikh (Code Review)
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Kyösti Mälkki (Code Review)