Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29257
Change subject: soc/amd/stoneyridge: SMBUS access through MMIO ......................................................................
soc/amd/stoneyridge: SMBUS access through MMIO
Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Create a CONFIG parameter, so user can decide if they want to use IO (default) or MMIO when accessing SMBUS.
BUG=b:117754784 TEST=
Change-Id: Id7accc33005a45ef31d260ad2499a4732b567242 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/include/soc/smbus.h 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29257/1
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index e676cc1..58ee1c7 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -20,8 +20,8 @@ #include <soc/iomap.h>
#if IS_ENABLED(CONFIG_STONEYRIDGE_MMIO_SMBUS) - #define SMB_RD(base, reg) read8((void*)SMBUS_MMIO_BASE + reg) - #define SMB_WR(value, base, reg) write8((void*)SMBUS_MMIO_BASE + reg, \ + #define SMB_RD(base, reg) read8((void *)SMBUS_MMIO_BASE + reg) + #define SMB_WR(value, base, reg) write8((void *)SMBUS_MMIO_BASE + reg, \ value) #else #define SMB_RD(base, reg) inb(base + reg)