Change in coreboot[4.11_branch]: src/mainboard/ocp/monolake: Set end of post GPIO

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54880 )

Change subject: src/mainboard/ocp/monolake: Set end of post GPIO
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src/mainboard/ocp/monolake: Set end of post GPIO

Set the end of post GPIO to the BMC. This gets IPMI working on the BMC.

Change-Id: I1a0055cdfd4a973b5f42570723bd95f1844dd9a7
Signed-off-by: Marc Jones 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54880
Tested-by: build bot (Jenkins) 
Reviewed-by: Stefan Reinauer 
---
M src/mainboard/ocp/monolake/mainboard.c
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Stefan Reinauer: Looks good to me, approved

diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
index 5f3408e..7887bae 100644
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ b/src/mainboard/ocp/monolake/mainboard.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */

+#include <bootstate.h>
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <cf9_reset.h>
@@ -22,6 +23,7 @@
 #include <drivers/vpd/vpd.h>
 #include <console/console.h>
 #include <drivers/ipmi/ipmi_ops.h>
+#include <gpio.h>
 #include "ipmi.h"
 /* VPD variable for enabling/disabling FRB2 timer. */
 #define FRB2_TIMER "FRB2_TIMER"
@@ -232,3 +234,13 @@
    else
    	return CONFIG_MAINBOARD_SERIAL_NUMBER;
 }
+
+/* Set the BMC BIOS POST complete GPIO (FM_BIOS_POST_CMPLT_N) on payload load. */
+static void bmc_set_post_complete_gpio_callback(void *arg)
+{
+	/* GPIO 46 FM_BIOS_POST_CMPLT_N */
+	gpio_set(46, 0);
+	printk(BIOS_DEBUG, "BMC: POST complete gpio set\n");
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, bmc_set_post_complete_gpio_callback, NULL);