Change in coreboot[master]: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21749

Change subject: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge
......................................................................

amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge

Duplicate existing pm_read and pm_write and create 32-bit register
access functions.

Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21749/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 054b36a..09dfb54 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -195,8 +195,10 @@
 void lpc_wideio_16_window(uint16_t base);
 u8 pm_read8(u8 reg);
 u16 pm_read16(u8 reg);
+u32 pm_read32(u8 reg);
 void pm_write8(u8 reg, u8 value);
 void pm_write16(u8 reg, u16 value);
+void pm_write32(u8 reg, u32 value);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 655a15a..a829575 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -60,6 +60,16 @@
    return read16((void *)(PM_MMIO_BASE + reg));
 }

+void pm_write32(u8 reg, u32 value)
+{
+	write32((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u32 pm_read32(u8 reg)
+{
+	return read32((void *)(PM_MMIO_BASE + reg));
+}
+
 void sb_enable(device_t dev)
 {
    printk(BIOS_DEBUG, "%s\n", __func__);