Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Avoid ROM area ......................................................................
nb/intel/i440bx: Avoid ROM area
Declare the ROM area to be read only in ACPI, and excludes it from ranges available for MMIO.
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui buurin@gmail.com --- M src/northbridge/intel/i440bx/acpi/i440bx.asl M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41091/1
diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl index e1e4e61..70c3aaa 100644 --- a/src/northbridge/intel/i440bx/acpi/i440bx.asl +++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl @@ -26,10 +26,26 @@ 0x00100000, // Address Base 0x00000000, // Address Length _Y00) + /* Reserved for firmware flash */ + Memory32Fixed (ReadOnly, + 0x100000000 - CONFIG_ROM_SIZE, // Address Base + CONFIG_ROM_SIZE, // Address Length + _Y01) }) CreateDWordField (BUF1, _Y00._LEN, EMLN) // _LEN: Length + CreateDWordField (BUF1, _Y01._BAS, FLSB) // _BAS: Base
+ /* + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + + /* Top of 4GB */ + ShiftLeft(0x10000000, 4, Local0) + FLSB = Local0 - CONFIG_ROM_SIZE; EMLN = _SB.PCI0.NB.TOM1 - 0x100000; - Return (BUF1) + Return (BUF1) /* _SB_.MEM1._CRS.BUF1 */ } } diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index e40b1fc..fa5948f 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -61,6 +61,7 @@ */ MM1B = _SB.PCI0.NB.TOM1 ShiftLeft(0x10000000, 4, Local0) + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B
Return(TMP)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Avoid ROM area ......................................................................
Patch Set 1: Code-Review+1
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
Patch Set 2:
This change is ready for review.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
Patch Set 2: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
Patch Set 4:
This needs to be adapted to the use of ASL 2 around it, I think
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41091
to look at the new patch set (#5).
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
nb/intel/i440bx: Make ROM area unavailable for MMIO
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui buurin@gmail.com --- M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41091/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41091 )
Change subject: nb/intel/i440bx: Make ROM area unavailable for MMIO ......................................................................
nb/intel/i440bx: Make ROM area unavailable for MMIO
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 98d06fb..a396a88 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -62,6 +62,7 @@ */ MM1B = _SB.PCI0.NB.TOM1 Local0 = 0x10000000 << 4 + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B
Return(TMP)
-
Angel Pons (Code Review) -
Keith Hui (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)