Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
soc/intel/tigerlake: Add pinmux support
TGL UPD value for selecting alternative native function pins. TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins have alternative pin selection for native fucntions. This UPD values are used by FSP for setting alternative pin selecting and mux for these pins.
BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board
Change-Id: I51deba87fcd1cde248e0f73757acf97682879090 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38452/1
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 62de63f..4fd2169 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -382,4 +382,46 @@ #define TOTAL_GPIO_COMM (COMM_5 + 1) #define TOTAL_PADS 294
+/* + * TGL UPD value for selecting alternative native function pins. + * TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins + * have alternative pin selection for native fucntions. + * This UPD values are used by FSP for setting alternative pin selecting and mux for these pins. + */ + +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_C8 0x190B0208 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_F1 0x290C0201 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_C9 0x190B1209 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_F2 0x290C1202 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_C10 0x190B220A +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_F0 0x290C2200 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_C11 0x190B320B +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_F3 0x290C3203 + +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8 0x1947CC08 +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_D13 0x3948CC0D +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9 0x1947AC09 +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_D14 0x3948AC0E + +#define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6 0x29460C06 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_A7 0x59420C07 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2 0x29461402 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_A13 0x5942140D +#define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7 0x29460407 +#define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_A8 0x59420408 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4 0x29460E04 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_A9 0x59420E09 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3 0x29461603 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_A14 0x5942160E +#define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5 0x29460605 +#define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_A10 0x5942060A + +#define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_A8 0x2942E408 +#define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_F4 0x194CE404 + +#define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_A9 0x2942E609 +#define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_A9 0x3942E609 +#define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_F5 0x294CE605 +#define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_F5 0x394CE605 + #endif
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 3: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/38452/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38452/3//COMMIT_MSG@12 PS3, Line 12: This These
https://review.coreboot.org/c/coreboot/+/38452/3/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/3/src/soc/intel/tigerlake/inc... PS3, Line 389: This These
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38452/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38452/3//COMMIT_MSG@12 PS3, Line 12: This
These
Ack
https://review.coreboot.org/c/coreboot/+/38452/3/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/3/src/soc/intel/tigerlake/inc... PS3, Line 389: This
These
Ack
Hello Patrick Rudolph, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38452
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
soc/intel/tigerlake: Add pinmux support
TGL UPD value for selecting alternative native function pins. TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins have alternative pin selection for native fucntions. These UPD values are used by FSP for setting alternative pin selecting and mux for these pins.
BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board
Change-Id: I51deba87fcd1cde248e0f73757acf97682879090 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38452/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38452/4//COMMIT_MSG@13 PS4, Line 13: selecting selection?
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38452/4//COMMIT_MSG@13 PS4, Line 13: selecting
selection?
Ack
Hello Patrick Rudolph, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38452
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
soc/intel/tigerlake: Add pinmux support
TGL UPD value for selecting alternative native function pins. TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins have alternative pin selection for native fucntions. These UPD values are used by FSP for setting alternative pin selection and mux for these pins.
BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board
Change-Id: I51deba87fcd1cde248e0f73757acf97682879090 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38452/6
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 7: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 7: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 7:
@aamir, can you please take a look into this
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 9: Code-Review-1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 297: * mux for these pins. Why? I don't understand why this is needed. We should be able to configure the pins natively. All these magic numbers look just like register values which is likely assuming a certain use which may not be in alignment with board design.
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 300: VER2 What does this mean?
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 301: 0x290C0201 What do these magic values represent?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 297: * mux for these pins.
Why? I don't understand why this is needed. We should be able to configure the pins natively. […]
Current TGL FSP configures all native function based on IP enable UPD and there is no way to skip FSP pin mux. And for these special pins like UART0, I2S4, DMIC, CnviRfReset and CnviClkreq, FSP use addtional UPD with predefined values. https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
And we need to provide UPD for these special pins like below, otherwise FSP will abort during FSP initialization. Refer below UPD setting for these pins( UART0, I2S4, DMIC, CnviRfReset and CnviClkreq,) https://chrome-internal.googlesource.com/chromeos/third_party/coreboot-intel...
We'raised up internal feature request to bypass FSP pin mux and FSP team will provide proposal soon. The request is creating one UPD in FSPm, FSPs for bypassing pin mux so that it's working as previous platform. And we'll also discuss special pin mux like UART0, I2S4, DMIC, CnviRfReset and CnviClkreq.
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 300: VER2
What does this mean?
This is defined in FSP definition. Ver2 is used for TGL LP. https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 301: 0x290C0201
What do these magic values represent?
According to current FSP code, it seems it's not just DW0 value but it's used for define GPIO Pad(physical pad) and native function by FSP internal pin mux logic. We'll ask more info in EDS when we discuss FSP pin mux bypassing option with FSP team.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 10: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 297: * mux for these pins.
Current TGL FSP configures all native function based on IP enable UPD and there is no way to skip FS […]
I ran a quick test last week where I skipped setting all the PinMux UPDs and I did not run into any abort (This test was done with FSP debug disabled). Can you please verify this at your end.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/11/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/11/src/soc/intel/tigerlake/in... PS11, Line 388: * CNVi pins have alternative pin selection for native fucntions. 'fucntions' may be misspelled - perhaps 'functions'?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/12/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/12/src/soc/intel/tigerlake/in... PS12, Line 388: * CNVi pins have alternative pin selection for native fucntions. 'fucntions' may be misspelled - perhaps 'functions'?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38452/13/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/13/src/soc/intel/tigerlake/in... PS13, Line 388: * CNVi pins have alternative pin selection for native fucntions. 'fucntions' may be misspelled - perhaps 'functions'?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 13: Code-Review-1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 13:
Abandon this patch
Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Abandoned
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