Attention is currently required from: Meera Ravindranath.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58178 )
Change subject: mb/intel/adlrvp: Fix S0ix regression
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
@Meera, this CL caused boot from CPU PCIe failed regression due to CLKSRC_3 is not set to disable. […]
I have verified this regression on LP4 ADL-P RVP.
Kindly refer to ADL-P RVP HAS it has details why do should keep this RP and CLKSRC enabled.
# Enable CPU PCIE RP 2 using CLK 3
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_req = 3,
.clk_src = 3,
}"
Prior to your CL:
Clock[3] Usage= 41
Clock[3] ClkReq= 3
With your CL:
Clock[3] Usage= FF
Clock[3] ClkReq= FF
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