Change in coreboot[master]: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61588 )
Change subject: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function ......................................................................
soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config` override function from Alder Lake SoC as the required config (SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock configuration using SMM is not enabled.
BUG=b:208827718 TEST=Able to built and boot brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 --- M src/soc/intel/alderlake/gpio.c 1 file changed, 0 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61588/1
diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index bf067b2..dc5847d 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -265,60 +265,3 @@ *num = ARRAY_SIZE(routes); return routes; }; - -/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */ -static const struct gpio_lock_config gpios_to_lock[] = { - { GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */ - { GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */ - { GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */ - { GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */ - { GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */ - { GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */ - { GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */ - { GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */ - { GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */ - { GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */ - { GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */ - { GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */ - { GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */ - { GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */ - { GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */ - { GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */ - { GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */ - { GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */ - { GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */ - { GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */ - { GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */ - { GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */ - { GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */ - { GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */ - { GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */ - { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ - { GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */ - { GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */ - - { GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */ - { GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */ - { GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */ - { GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */ - { GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */ - { GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */ - { GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */ - { GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */ - { GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */ - { GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */ - { GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */ - { GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */ - { GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */ - { GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */ - { GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */ - { GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */ - - { GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */ -}; - -const struct gpio_lock_config *soc_gpio_lock_config(size_t *num) -{ - *num = ARRAY_SIZE(gpios_to_lock); - return gpios_to_lock; -}
-
Subrata Banik (Code Review)