New patch to review for coreboot: dc097d6 exynos5420: Clock the mmc blocks off of the mpll.

[Gabe Black]

Gabe Black ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3703

-gerrit

commit dc097d6fe319c58d68de65aa6e252675098ac418
Author: Gabe Black 
Date:   Mon Jun 24 03:14:41 2013 -0700

exynos5420: Clock the mmc blocks off of the mpll.

The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
    been set to use a different pll. This changes them over and modifies the
    divider so that the frequency stays the same.

Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
    Signed-off-by: Gabe Black 
---
 src/cpu/samsung/exynos5420/setup.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 7d63772..e89ed8e 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -222,7 +222,7 @@ struct exynos5_phy_control;
 #define CLK_DIV_CPU0_VAL	0x01440020

/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL	0x12221222
+#define CLK_SRC_TOP0_VAL	0x12222222
 #define CLK_SRC_TOP1_VAL	0x00100200
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
@@ -231,7 +231,7 @@ struct exynos5_phy_control;
 #define CLK_SRC_TOP7_VAL	0x00022200

/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL	0x23712311
+#define CLK_DIV_TOP0_VAL	0x23713311
 #define CLK_DIV_TOP1_VAL	0x13100B00
 #define CLK_DIV_TOP2_VAL	0x11101100