[XS] Change in coreboot[main]: soc/intel/pantherlake: Add config option to limit DRAM frequency

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85101?usp=email )

Change subject: soc/intel/pantherlake: Add config option to limit DRAM frequency
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soc/intel/pantherlake: Add config option to limit DRAM frequency

This patch adds a new config option to limit the maximum DRAM
frequency for Pantherlake platforms.

The mainboard code should try to set `max_dram_speed_mts` from
override device tree if required.

BUG=b:373394046
TEST=Able to build and boot google/fatcat.

Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/romstage/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/85101/1

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index b59ce5e..5846037 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -512,6 +512,8 @@
     */
    uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];

+	uint16_t max_dram_speed_mts;
+
 };

typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index b105d3d..e6ed19ec 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -74,6 +74,9 @@
    		m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
    }

+	if (config->max_dram_speed_mts)
+		m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
+
    m_cfg->RMT = config->rmt;
    m_cfg->MrcFastBoot = 1;
 }