Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39756 )
Change subject: nb/intel/sandybridge: Add warning to saved structs ......................................................................
nb/intel/sandybridge: Add warning to saved structs
When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted.
Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/39756/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 34fb499..dc99913 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -33,8 +33,6 @@ #include "raminit_common.h" #include "sandybridge.h"
-#define MRC_CACHE_VERSION 1 - /* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 516d8f5..18a69af 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -41,15 +41,22 @@ performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4
+/* + * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! + */ +#define MRC_CACHE_VERSION 1 + typedef struct odtmap_st { u16 rttwr; u16 rttnom; } odtmap;
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct dimm_info_st { dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; } dimm_info;
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ struct ram_rank_timings { /* ROUNDT_LAT register: One byte per slotrank */ u8 roundtrip_latency; @@ -72,6 +79,7 @@ } lanes[NUM_LANES]; };
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int sandybridge;
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39756 )
Change subject: nb/intel/sandybridge: Add warning to saved structs ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39756 )
Change subject: nb/intel/sandybridge: Add warning to saved structs ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39756 )
Change subject: nb/intel/sandybridge: Add warning to saved structs ......................................................................
nb/intel/sandybridge: Add warning to saved structs
When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted.
Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 34fb499..dc99913 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -33,8 +33,6 @@ #include "raminit_common.h" #include "sandybridge.h"
-#define MRC_CACHE_VERSION 1 - /* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 516d8f5..18a69af 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -41,15 +41,22 @@ performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4
+/* + * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! + */ +#define MRC_CACHE_VERSION 1 + typedef struct odtmap_st { u16 rttwr; u16 rttnom; } odtmap;
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct dimm_info_st { dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; } dimm_info;
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ struct ram_rank_timings { /* ROUNDT_LAT register: One byte per slotrank */ u8 roundtrip_latency; @@ -72,6 +79,7 @@ } lanes[NUM_LANES]; };
+/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int sandybridge;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39756 )
Change subject: nb/intel/sandybridge: Add warning to saved structs ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1636 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1635 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1634 Non-emulation targets: HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1638 HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1637
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)