Change in coreboot[master]: soc/amd/cezanne: populate some FSP-M UPDs

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 )

Change subject: soc/amd/cezanne: populate some FSP-M UPDs
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Patch Set 3:

(2 comments)

File src/soc/amd/cezanne/romstage.c:

https://review.coreboot.org/c/coreboot/+/50239/comment/cf484666_d43faae0 
PS2, Line 19: 1
> ah, DRIVERS_UART_8250MEM and DRIVERS_UART_8250MEM_32 only get selected together, so this is indeed f […]

Done

https://review.coreboot.org/c/coreboot/+/50239/comment/dd383286_68289e74 
PS2, Line 19: serial_port_stride
> Do we need to pass in the baud clock? Or does FSP-M assume the baud rate has already been set?

added that to match what picasso does for now; since during bringup we'll only use the internal uart the defaults were sane though. refclk, baudrate and stride will probably be removed after the initial bringup is done