Change in coreboot[master]: mb/ocp/tiogapass: Enable IPMI KCS

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

mb/ocp/tiogapass: Enable IPMI KCS

Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin

Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38995/1

diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
index ab0f789..41abb65 100644
--- a/src/mainboard/ocp/tiogapass/Kconfig
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -26,6 +26,7 @@
    select SOC_INTEL_XEON_SP
    select MAINBOARD_USES_FSP2_0
    select FSP_CAR
+	select IPMI_KCS

config MAINBOARD_DIR
    string
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
index 3ac0f56..decb81b 100644
--- a/src/mainboard/ocp/tiogapass/devicetree.cb
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -53,6 +53,8 @@
   register "coherency_support" = "1"
   register "ats_support" = "1"

+  register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
   device cpu_cluster 0 on
     device lapic 0 on end
   end
@@ -83,7 +85,13 @@
    	device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
    	device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
    	device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
-		device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.0 on
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+		end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
    	device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
    	device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
    	device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@8 
PS1, Line 8: 
Mention why you chose a timeout of 60 seconds.

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@9 
PS1, Line 9: Tested on OCP Tioga Pass.
Please add a blank line, or use TEST= line.

Please be more specific, how you tested this.

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@11 
PS1, Line 11: 
Please remove the blank line.

[Johnny Lin (Code Review)]

Hello Andrey Petrov, Patrick Rudolph, Jingle Hsu, Morgan Jang, Jonathan Zhang, David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38995

to look at the new patch set (#2).

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

mb/ocp/tiogapass: Enable IPMI KCS

A bigger than zero value of bmc_boot_timeout must be set
for KCS ipmi_get_bmc_self_test_result() to run, otherwise
the self test result will be error and won't write SMBIOS
type 38 table. Here we set 60 seconds as the maximal self
test timeout.

Tested=Check if the BMC IPMI response data and SMBIOS type
38 on OCP Tioga Pass are correct or not.

Signed-off-by: Johnny Lin 
Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38995/2

[Johnny Lin (Code Review)]

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@8 
PS1, Line 8:
> Mention why you chose a timeout of 60 seconds.

Done

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@9 
PS1, Line 9: Tested on OCP Tioga Pass.
> Please add a blank line, or use TEST= line. […]

Done

https://review.coreboot.org/c/coreboot/+/38995/1//COMMIT_MSG@11 
PS1, Line 11:
> Please remove the blank line.

Done

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

Patch Set 2: Code-Review+1

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38995

to look at the new patch set (#3).

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

mb/ocp/tiogapass: Enable IPMI KCS

A bigger than zero value of bmc_boot_timeout must be set
for KCS ipmi_get_bmc_self_test_result() to run, otherwise
the self test result will be error and won't write SMBIOS
type 38 table. Here we set 60 seconds as the maximal self
test timeout.

Tested=Check if the BMC IPMI response data and SMBIOS type
38 on OCP Tioga Pass are correct or not.

Signed-off-by: Johnny Lin 
Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38995/3

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

Patch Set 4: Code-Review+2

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38995

to look at the new patch set (#11).

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

mb/ocp/tiogapass: Enable IPMI KCS

A bigger than zero value of bmc_boot_timeout must be set
for KCS ipmi_get_bmc_self_test_result() to run, otherwise
the self test result will be error and won't write SMBIOS
type 38 table. Here we set 60 seconds as the maximal self
test timeout.

Tested=Check if the BMC IPMI response data and SMBIOS type
38 on OCP Tioga Pass are correct or not.

Signed-off-by: Johnny Lin 
Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38995/11

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38995 )

Change subject: mb/ocp/tiogapass: Enable IPMI KCS
......................................................................

mb/ocp/tiogapass: Enable IPMI KCS

A bigger than zero value of bmc_boot_timeout must be set
for KCS ipmi_get_bmc_self_test_result() to run, otherwise
the self test result will be error and won't write SMBIOS
type 38 table. Here we set 60 seconds as the maximal self
test timeout.

Tested=Check if the BMC IPMI response data and SMBIOS type
38 on OCP Tioga Pass are correct or not.

Signed-off-by: Johnny Lin 
Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
index b3b43fb..9dbc066 100644
--- a/src/mainboard/ocp/tiogapass/Kconfig
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -22,6 +22,7 @@
    select SOC_INTEL_XEON_SP
    select MAINBOARD_USES_FSP2_0
    select FSP_CAR
+	select IPMI_KCS

config MAINBOARD_DIR
    string
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
index 4a5bb1d..c2eddf2 100644
--- a/src/mainboard/ocp/tiogapass/devicetree.cb
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -51,6 +51,8 @@
    register "coherency_support" = "1"
    register "ats_support" = "1"

+	register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
    device cpu_cluster 0 on
      device lapic 0 on end
    end
@@ -81,7 +83,13 @@
    	device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
    	device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
    	device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
-		device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.0 on
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+		end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
    	device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
    	device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
    	device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller