Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__ ......................................................................
intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__
Either the files are only built for ramstage, or garbage collection takes care of it otherwise.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 7 files changed, 1 insertion(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/1
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7b..c6c88cf 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include <cpu/intel/microcode.h> #include <cf9_reset.h>
-#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__
/* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,7 +111,6 @@ /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */
volatile u8 *find_fsp() { @@ -225,8 +220,6 @@ } #endif /* FSP_RESERVE_MEMORY_SIZE */
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) {
if (fsp_header_ptr == NULL) @@ -249,7 +242,6 @@ (u8)(fsp_header_ptr->ImageRevision & 0xff)); }
- #if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM @@ -363,4 +355,3 @@ /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9..a02e34d 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -79,9 +79,7 @@
struct mrc_data_container *find_current_mrc_cache(void);
-#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif
#endif
@@ -99,9 +97,7 @@ #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6
-#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif
#define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6da1258..3e2499a 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -29,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif
static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -61,8 +59,6 @@ 52, 53, 59, 40 }; /* [40:43] */
-#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -253,7 +249,6 @@ printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */
/** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b1..fa2f508 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -51,7 +51,6 @@ int bridge_silicon_revision(void); void rangeley_early_initialization(void);
-#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,7 +59,6 @@
void report_platform_info(void);
-#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */
#endif /* __ACPI__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d..1f318b3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -21,8 +21,6 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif
-void report_platform_info(void); - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f0..2b5dad7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <soc/iosf.h> -#include <soc/romstage.h> +#include <soc/baytrail.h> #include <cpu/x86/msr.h> #include <soc/msr.h> #include <cpu/x86/name.h> diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543..bbcf753 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif
/** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif }
/**
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#2).
Change subject: intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__ ......................................................................
intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__
Either the files are only built for ramstage, or garbage collection takes care of it otherwise.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 7 files changed, 7 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/2
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp_baytrail: Remove uses of __PRE_RAM__ ......................................................................
Patch Set 3: Code-Review+1
Hello Patrick Rudolph, David Guckian, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#4).
Change subject: intel/fsp1_0, baytrail: Tidy up use of preprocessor ......................................................................
intel/fsp1_0, baytrail: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 8 files changed, 14 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/4
Hello Patrick Rudolph, David Guckian, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#5).
Change subject: intel/fsp1_0, baytrail: Tidy up use of preprocessor ......................................................................
intel/fsp1_0, baytrail: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 8 files changed, 14 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/5
Hello Patrick Rudolph, David Guckian, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#7).
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/ramstage.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/soc.h M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 25 files changed, 40 insertions(+), 132 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34928/7/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/soc.h:
https://review.coreboot.org/c/coreboot/+/34928/7/src/southbridge/intel/fsp_r... PS7, Line 55: void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); "foo * bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/34928/7/src/southbridge/intel/fsp_r... PS7, Line 55: void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); "foo * bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/34928/7/src/southbridge/intel/fsp_r... PS7, Line 69: int smbus_read_byte(unsigned device, unsigned address); Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/c/coreboot/+/34928/7/src/southbridge/intel/fsp_r... PS7, Line 69: int smbus_read_byte(unsigned device, unsigned address); Prefer 'unsigned int' to bare use of 'unsigned'
Hello Patrick Rudolph, David Guckian, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#8).
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/ramstage.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/soc.h M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 25 files changed, 41 insertions(+), 132 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/8
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
Patch Set 8: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
Patch Set 9: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: David Guckian Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/ramstage.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/soc.h M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 25 files changed, 41 insertions(+), 132 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 34761a0..7eba875 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -116,10 +116,6 @@ return mrc_cache; }
-/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ -#if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -221,8 +217,6 @@ current->mrc_data_size + sizeof(*current), current); }
-#endif /* !defined(__PRE_RAM__) */ - void *find_and_set_fastboot_cache(void) { struct mrc_data_container *mrc_cache = NULL; diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7b..a7f3017 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include <cpu/intel/microcode.h> #include <cf9_reset.h>
-#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__
/* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,12 +111,10 @@ /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */
volatile u8 *find_fsp() { - -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE volatile register u8 *fsp_ptr asm ("eax");
/* Entry point for CAR assembly routine */ @@ -130,7 +124,7 @@ ); #else volatile u8 *fsp_ptr; -#endif /* __PRE_RAM__ */ +#endif
/* The FSP is stored in CBFS */ fsp_ptr = (u8 *) CONFIG_FSP_LOC; @@ -225,8 +219,6 @@ } #endif /* FSP_RESERVE_MEMORY_SIZE */
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) {
if (fsp_header_ptr == NULL) @@ -249,12 +241,10 @@ (u8)(fsp_header_ptr->ImageRevision & 0xff)); }
- -#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ -int save_mrc_data(void *hob_start) +static int save_mrc_data(void *hob_start) { u32 *mrc_hob; u32 *mrc_hob_data; @@ -307,7 +297,6 @@ hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); return (1); } -#endif /* CONFIG_ENABLE_MRC_CACHE */
static void find_fsp_hob_update_mrc(void *unused) { @@ -319,13 +308,13 @@ } else { /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); + }
- #if CONFIG(ENABLE_MRC_CACHE) + if (CONFIG(ENABLE_MRC_CACHE)) { if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif } }
@@ -356,11 +345,10 @@ printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); }
+ /* Set up for the ramstage FSP calls */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
/* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9..a368c7f 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -21,10 +21,7 @@
#include "fsp_values.h"
-#if CONFIG(ENABLE_MRC_CACHE) -int save_mrc_data(void *hob_start); void *find_and_set_fastboot_cache(void); -#endif
volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); @@ -65,7 +62,6 @@ #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
-#if CONFIG(ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -79,11 +75,7 @@
struct mrc_data_container *find_current_mrc_cache(void);
-#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif - -#endif
/* The offset in bytes from the start of the info structure */ #define FSP_IMAGE_SIG_LOC 0 @@ -99,9 +91,7 @@ #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6
-#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif
#define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 04a696c..43e71f4 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -26,12 +26,6 @@ #include <fspbootmode.h> #include "../chip.h"
-#ifdef __PRE_RAM__ -#include <southbridge/intel/fsp_rangeley/romstage.h> -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -96,9 +90,9 @@ if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if CONFIG(ENABLE_FSP_FAST_BOOT) - UpdData->PcdFastboot = UPD_ENABLE; -#endif + if (CONFIG(ENABLE_FSP_FAST_BOOT)) + UpdData->PcdFastboot = UPD_ENABLE; + /* * Loop through all the SOC devices in the devicetree * enabling and disabling them as requested. @@ -164,5 +158,3 @@
return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c..5038bf8 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -40,5 +40,6 @@
/* Read BCLK from MSR */ unsigned bus_freq_khz(void); +void set_max_freq(void);
#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index d20859d..f98a79b 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -23,7 +23,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3dc24f0..8ea2d69 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -35,12 +35,6 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif
#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cf6a856..7a413d9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -36,6 +36,7 @@ #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> +#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/romstage.h> @@ -131,7 +132,8 @@
tco_disable();
- byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable();
console_init();
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index f9c3014..5b2d135 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -47,13 +47,6 @@ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; }
-#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include <soc/ramstage.h> -#else -#include <soc/romstage.h> -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +69,3 @@
wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 7fe8f70..0c86ce3 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -29,6 +29,7 @@ #include <cpu/x86/smm.h> #include <reg_script.h>
+#include <soc/baytrail.h> #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index f11b206..48f0cdd 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -31,12 +31,6 @@ #include <soc/iomap.h> #include <soc/smm.h>
-#ifdef __PRE_RAM__ -#include <soc/romstage.h> -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { @@ -307,10 +301,9 @@ ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL;
-#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif + if (CONFIG(ENABLE_MRC_CACHE)) + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
if (prev_sleep_state == ACPI_S3) { /* S3 resume */ @@ -335,5 +328,3 @@
return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6da1258..3e2499a 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -29,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif
static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -61,8 +59,6 @@ 52, 53, 59, 40 }; /* [40:43] */
-#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -253,7 +249,6 @@ printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */
/** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b1..3a2fcaa 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -35,23 +35,24 @@ #else #define DEFAULT_RCBA 0xfed1c000 #endif -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__
/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define SKPAD 0xFC
/* SOC types */ #define SOC_TYPE_BAYTRAIL 0x0F1C
+/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } +#include <device/device.h>
-#define SKPAD 0xFC +static inline void barrier(void) { asm("" ::: "memory"); }
int bridge_silicon_revision(void); void rangeley_early_initialization(void); +void set_max_freq(void);
-#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,8 +61,7 @@
void report_platform_info(void);
-#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ - #endif /* __ACPI__ */ + #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 75daba5..71c8e10 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,6 +283,8 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
+uint32_t chipset_prev_sleep_state(uint32_t clear); + #if CONFIG(ELOG) void southcluster_log_state(void); #else diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h index e8f81bb..45fda9e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h @@ -22,7 +22,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d..dce9539 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -17,31 +17,18 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_
-#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - -void report_platform_info(void); - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h>
void main(FSP_INFO_HEADER *fsp_info_header); -uint32_t chipset_prev_sleep_state(uint32_t clear);
#define NUM_ROMSTAGE_TS 4
void tco_disable(void); void punit_init(void); -void set_max_freq(void); void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif
#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f0..2b5dad7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <soc/iosf.h> -#include <soc/romstage.h> +#include <soc/baytrail.h> #include <cpu/x86/msr.h> #include <soc/msr.h> #include <cpu/x86/name.h> diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 35b531a..f347591 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -167,7 +167,8 @@ tco_disable();
post_code(0x42); - byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable();
post_code(0x43); console_init(); diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index f9c3014..6605575 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -17,6 +17,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/msr.h> +#include <soc/baytrail.h>
unsigned bus_freq_khz(void) { @@ -47,13 +48,6 @@ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; }
-#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include <soc/ramstage.h> -#else -#include <soc/romstage.h> -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +70,3 @@
wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index aeb2d9b..5605d41 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <version.h> +#include "chip.h"
/** diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d7ae8f6..5693bb7 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -33,6 +33,7 @@ #include <string.h> #include <cbmem.h> #include <arch/acpigen.h> +#include "chip.h" #include "soc.h" #include "irq.h" #include "nvs.h" diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 5827b0f..7921d80 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -17,10 +17,6 @@ #ifndef _RANGELEY_ROMSTAGE_H_ #define _RANGELEY_ROMSTAGE_H_
-#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 58388a2..604c566 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" #include "soc.h"
typedef struct southbridge_intel_fsp_rangeley_config config_t; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index aceb425..ce5e056 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -47,29 +47,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
-#if defined(__SMM__) && !defined(__ASSEMBLER__) void intel_soc_finalize_smm(void); + +#if !defined(__ROMCC__) +#include <device/device.h> +void soc_enable(struct device *dev); +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); #endif
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include "chip.h" int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev);
-void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
-#if CONFIG(ELOG) void soc_log_state(void); -#endif -#else void enable_smbus(void); void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); void rangeley_sb_early_initialization(void); -#endif + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned int device, unsigned int address); #endif
#define MAINBOARD_POWER_OFF 0 diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543..bbcf753 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif
/** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif }
/**
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