Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28608

Change subject: amd/stoneyridge: Sync PSP base to MSR
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amd/stoneyridge: Sync PSP base to MSR

According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address.  Read the value from the PSP's
config space and sync each core's copy of the MSR to match.

BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg

Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/cpu.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/28608/1

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 43ee6a0..8e2703d 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -121,6 +121,15 @@
 {
    check_mca();
    setup_lapic();
+
+	/* Per AMD, sync an undocumented MSR with the PSP base address */
+	msr_t psp_msr;
+	uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
+	psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
+	psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	psp_msr.hi = 0;
+	psp_msr.lo = psp_bar;
+	wrmsr(0xc00110a2, psp_msr);
 }

static struct device_operations cpu_dev_ops = {