Attention is currently required from: Mario Scheithauer, Werner Zeh.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73766 )
Change subject: soc/intel/elkhartlake: Make PCIe root port speed limit configurable
......................................................................
Patch Set 1: Code-Review+1
--
To view, visit
https://review.coreboot.org/c/coreboot/+/73766
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc
Gerrit-Change-Number: 73766
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer
mario.scheithauer@siemens.com
Gerrit-Reviewer: Lean Sheng Tan
sheng.tan@9elements.com
Gerrit-Reviewer: Maximilian Brune
maximilian.brune@9elements.com
Gerrit-Reviewer: Werner Zeh
werner.zeh@siemens.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Attention: Mario Scheithauer
mario.scheithauer@siemens.com
Gerrit-Attention: Werner Zeh
werner.zeh@siemens.com
Gerrit-Comment-Date: Mon, 20 Mar 2023 22:50:01 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment