[M] Change in coreboot[master]: cpu/intel/speedstep: Separate single SSDT CPU entry

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74400 )

Change subject: cpu/intel/speedstep: Separate single SSDT CPU entry
......................................................................

cpu/intel/speedstep: Separate single SSDT CPU entry

Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/cpu/intel/speedstep/acpi.c
M src/southbridge/intel/i82371eb/acpi_tables.c
2 files changed, 70 insertions(+), 40 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 0d2cc87..0a13445 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -70,53 +70,61 @@
    return SW_ANY;
 }

+static void generate_cpu_entry(int cpu, int core, int cores_per_package)
+{
+	int pcontrol_blk = PMB0_BASE, plen = 6;
+
+	static struct {
+		int once;
+		uint8_t coordination;
+		int num_cstates;
+		const acpi_cstate_t *cstates;
+		sst_table_t pstates;
+	} s;
+
+	if (!s.once) {
+		s.once = 1;
+		s.coordination = get_p_state_coordination();
+		s.num_cstates = get_cst_entries(&s.cstates);
+		speedstep_gen_pstates(&s.pstates);
+	}
+
+	if (core > 0) {
+		pcontrol_blk = 0;
+		plen = 0;
+	}
+
+	/* Generate processor _SB.CPUx. */
+	acpigen_write_processor(cpu * cores_per_package + core, pcontrol_blk, plen);
+
+	/* Generate p-state entries. */
+	gen_pstate_entries(&s.pstates, cpu, cores_per_package, s.coordination);
+
+	/* Generate c-state entries. */
+	if (s.num_cstates > 0)
+		acpigen_write_CST_package(s.cstates, s.num_cstates);
+
+	acpigen_pop_len();
+}
+
 /**
  * @brief Generate ACPI entries for Speedstep for each cpu
  */
 void generate_cpu_entries(const struct device *device)
 {
-	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
    int totalcores = dev_count_cpu();
-	int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
-	int numcpus = totalcores/cores_per_package; /* This assumes that all
-						       CPUs share the same
-						       layout. */
+	int cores_per_package = (cpuid_ebx(1) >> 16) & 0xff;

-	int num_cstates;
-	const acpi_cstate_t *cstates;
-	sst_table_t pstates;
-	uint8_t coordination = get_p_state_coordination();
+	/* This assumes that all CPUs share the same layout. */
+	int numcpus = totalcores / cores_per_package;

printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
           numcpus, cores_per_package);

-	num_cstates = get_cst_entries(&cstates);
-	speedstep_gen_pstates(&pstates);
+	for (int cpu_id = 0; cpu_id < numcpus; ++cpu_id)
+		for (int core_id = 0; core_id < cores_per_package; core_id++)
+			generate_cpu_entry(cpu_id, core_id, cores_per_package);

-	for (cpuID = 0; cpuID < numcpus; ++cpuID) {
-		for (coreID = 1; coreID <= cores_per_package; coreID++) {
-			if (coreID > 1) {
-				pcontrol_blk = 0;
-				plen = 0;
-			}
-
-			/* Generate processor _SB.CPUx. */
-			acpigen_write_processor(
-					cpuID * cores_per_package + coreID - 1,
-					pcontrol_blk, plen);
-
-			/* Generate p-state entries. */
-			gen_pstate_entries(&pstates, cpuID,
-					cores_per_package, coordination);
-
-			/* Generate c-state entries. */
-			if (num_cstates > 0)
-				acpigen_write_CST_package(
-							cstates, num_cstates);
-
-			acpigen_pop_len();
-		}
-	}
    /* PPKG is usually used for thermal management
       of the first and only package. */
    acpigen_write_processor_package("PPKG", 0, cores_per_package);
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index cd002e8..a4cd1b3 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -6,18 +6,27 @@
 #include <device/device.h>
 #include "i82371eb.h"

+static void generate_cpu_entry(int cpu)
+{
+	int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6;
+
+	acpigen_write_processor(cpu, pcontrol_blk, plen);
+	acpigen_pop_len();
+}
+
 void generate_cpu_entries(const struct device *device)
 {
-	int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6;
+	int cpu;
    int numcpus = dev_count_cpu();
+
    printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);

/* without the outer scope, further ssdt addition will end up
     * within the processor statement */
    acpigen_write_scope("\_SB");
-	for (cpu=0; cpu < numcpus; cpu++) {
-		acpigen_write_processor(cpu, pcontrol_blk, plen);
-		acpigen_pop_len();
-	}
+
+	for (cpu = 0; cpu < numcpus; cpu++)
+		generate_cpu_entry(cpu);
+
    acpigen_pop_len();
 }