Change in ...coreboot[master]: post_code: add post code for video initialization failure

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32775 )

Change subject: post_code: add post code for video initialization failure
......................................................................

post_code: add post code for video initialization failure

Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M Documentation/POSTCODES
M src/drivers/intel/fsp2_0/silicon_init.c
M src/include/console/post_codes.h
3 files changed, 21 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index a9d392a..0e67dd1 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -21,6 +21,7 @@
 0xe2 Vendor binary (e.g. FSP) generated a fatal error
 0xe3 RAM could not be initialized
 0xe4 Critical hardware component could not initialize
+0xe5 Video subsystem failed to initialize
 0xf8 Entry into elf boot
 0xf3 Jumping to payload

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index b0a697d..e9c29db 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -18,6 +18,7 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <program_loading.h>
+#include <soc/intel/common/vbt.h>
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
@@ -29,6 +30,7 @@
    FSPS_UPD *upd, *supd;
    fsp_silicon_init_fn silicon_init;
    uint32_t status;
+	uint8_t postcode;

supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);

@@ -59,8 +61,18 @@
    /* Handle any errors returned by FspSiliconInit */
    fsp_handle_reset(status);
    if (status != FSP_SUCCESS) {
+		if (vbt_get()) {
+			/* Attempted to initialize graphics. Assume failure
+			 * is related to a video failure.
+			 */
+			postcode = POST_VIDEO_FAILURE;
+		} else {
+			/* Other silicon initialization failed */
+			postcode = POST_HW_INIT_FAILURE;
+		}
    	printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
-		die("FspSiliconINit returned an error!\n");
+		die_with_post_code(postcode,
+			"FspSiliconINit returned an error!\n");
    }
 }

diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index ae277d8..c1917ad 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -356,6 +356,13 @@
 #define POST_HW_INIT_FAILURE			0xe4

/**
+ * \brief Video failure
+ *
+ * Video subsystem failed to initialize.
+ */
+#define POST_VIDEO_FAILURE			0xe5
+
+/**
  * \brief TPM failure
  *
  * An error with the TPM, either unexepcted state or communications failure.