Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31339
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
cpu/intel/common: Add Nehalem for FSB detection
Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/common/fsb.c 1 file changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31339/1
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 9296785..83220de 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -39,8 +39,11 @@ case 0x17: /* Enhanced Core */ ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x25: /* Nehalem BCLK fixed at 133MHz */ + ret = 133; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ ret = 100;
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31339 )
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31339 )
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
Patch Set 1:
Turns out this file is built for soc/intel as well. So get_ia32_fsb() should handle those models too...
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31339 )
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31339 )
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31339 )
Change subject: cpu/intel/common: Add Nehalem for FSB detection ......................................................................
cpu/intel/common: Add Nehalem for FSB detection
Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/31339 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/common/fsb.c 1 file changed, 5 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 9296785..83220de 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -39,8 +39,11 @@ case 0x17: /* Enhanced Core */ ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x25: /* Nehalem BCLK fixed at 133MHz */ + ret = 133; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ ret = 100;
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)