Change in coreboot[master]: soc/intel/cannonlake: Drop unused LPC BIOS Control macro

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63688 )

Change subject: soc/intel/cannonlake: Drop unused LPC BIOS Control macro
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soc/intel/cannonlake: Drop unused LPC BIOS Control macro

This patch drops unused LPC BIOS control macros.

BUG=b:211954778
TEST=Able to build and boot google/hatch.

Signed-off-by: Subrata Banik 
Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63688
Tested-by: build bot (Jenkins) 
Reviewed-by: Lean Sheng Tan 
Reviewed-by: Eric Lai 
Reviewed-by: Angel Pons 
---
M src/soc/intel/cannonlake/include/soc/lpc.h
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Lean Sheng Tan: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index a510bc5..c16b732 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -24,10 +24,6 @@
 #define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
 #define LGMR			0x98 /* LPC Generic Memory Range */
-#define BIOS_CNTL		0xdc
-#define   LPC_BC_BILD		(1 << 7) /* BILD */
-#define   LPC_BC_LE		(1 << 1) /* LE */
-#define   LPC_BC_EISS		(1 << 5) /* EISS */
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.