Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email )
Change subject: Documentation: Add Erying Polestar G613 Pro ......................................................................
Documentation: Add Erying Polestar G613 Pro
Documentation entry has to be submitted with board tree that's currently being reviewed upstream.
Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Signed-off-by: Alicja Michalska ahplka19@gmail.com --- A Documentation/mainboard/erying/tgl_matx.md A Documentation/mainboard/erying/tgl_matx_board.jpg M Documentation/mainboard/index.md 3 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81611/1
diff --git a/Documentation/mainboard/erying/tgl_matx.md b/Documentation/mainboard/erying/tgl_matx.md new file mode 100644 index 0000000..d3d7f82 --- /dev/null +++ b/Documentation/mainboard/erying/tgl_matx.md @@ -0,0 +1,136 @@ +# Erying Polestar G613 Pro + +This page describes how to run coreboot on the [Erying Polestar G613 Pro]. + + + +## Required proprietary blobs + +To build full working image of coreboot, the following blobs are required: + +```{eval-rst} ++-----------------+---------------------------------+----------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+======================+ +| Microcode | CPU Microcode | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +| FSP-M & FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+----------------------+ +| ME | Intel Management Engine | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +| FD | Intel Flash Descriptor | Optional (if SI_BIOS)| ++-----------------+---------------------------------+----------------------+ +``` + +Microcode for those SoCs cannot be generated from the tree. +While boards with D1 (production) stepping may work, microcode Intel had +included in their tree is too old, which causes issues with APIC +(Advanced Programmable Interrupt Controller), resulting in overal instability. + +This is **required** for boards sold with D0 SoC revision (Engineering Sample). +Maintainer of this port had included publicly-available [microcodes] in +`3rdparty/blobs` coreboot repository, which are being pulled as submodule. + +To choose appropriate microcode for your system, you should choose: +1. If your motherboard uses Engineering Sample (D0) stepping: +- cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin +2. If your motherboard uses retail (D1) stepping: +- cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin + +Failure to choose an appropriate microcode may result in: +- Bricked (unbootable) board +- Issues with APIC, resulting in random freezes +- MCE (Machine Check Exception) errors +- Unstable system RAM, leading to bit flips and data corruption + +There are no extra steps required for FSP. +Both SKUs work perfectly with FSP Intel publishes in their public repository. +Coreboot automatically pulls FSP binary from `3rdparty/fsp` submodule at build +time, which points to TigerLakeFspBinPkg/Client package in official +Intel FSP repository. + +## Flashing coreboot + +### Internally + +Vendor of this motherboard hasn't locked any flash regions, resulting in +[flashrom] having full access to the SPI chip. +Assuming that user had booted Linux with `iomem=relaxed`, they can: +- flash coreboot from stock firmware +- flash stock firmware from coreboot +- update coreboot build to a newer version + +Without opening the case and connecting the SPI flasher. +Please note that for TigerLake Halo platform you will need to use +[flashrom] v1.3.0 or newer, as older versions won't detect the chipset. + +### Externally + +SPI chip on this motherboard is located right underneath the PCH heatsink. +Due to it's location, it's likely that you will need to move (or remove) the +PCH (Platform Controller Hub) heatsink in order to clip the chip properly. + +Vendor populated this board with Winbond W25Q128FV chip in SOIC-8 package. +Although the stock chip is 16MiB, it is possible to replace it with 32MiB +equivalent if user desires to use LinuxBoot payload instead of EDK2. + +Please note that SPI voltage on this board is standard 3.3V, despite using mobile SoC and PCH. + +## Tested and working + +- RS232 serial output from IT8613E for debugging (cbmem, Linux) +- Fan control from userspace (IT8613E Environment Controller) +- USB2.0 and 3.0 +- HDMI (iGPU, including audio) +- Realtek RTL8111 (GbE NIC) +- Realtek ALC897 (integrated audio) +- PCI-E x16 4.0 (SoC) +- M.2 x4 4.0 (SoC) +- M.2 x3 3.0 (PCH) +- 4x SATA3 ports +- IOMMU/VT-x (PCI-E passthrough) +- PCI-E ReBAR (Resizable BAR) + +## Work in progress/broken/issues + +- XMP Profiles (memory controller in pre-production silicon causes instability) +- GPU GOP (most EDK2 branches don't include module to load external OpROMs) +- Sleep states (also broken on stock, system loses RAM power in S3 state) +- USB3.2 might take few tries to get detected at full speed +- iGPU DisplayPort (simple fix, need to re-configure GPIOs) +- Automatic fan control (fans will always spin at 50%) +- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet) +- PCI-E ASPM (results in AER spam in dmesg) +- M.2 NGFF (WiFi) - untested, should work +- Intel PTT (fTPM) + +Please ensure to: +- Disable sleep state in your OS to prevent data loss +- Configure automatic fan control using pwmconfig (`modprobe it87 force_id=0x8603) + +## Notes +- Intel Management Engine blob is required, as it manages: PMC (Power Management Controller), SA (System Agent), USB Controller and many more. +System Agent manages critical components, such as memory controller or PCI-E lane bifurfication. Therefore, system will simply not POST without this blob present in the build. +Blob included in `3rdparty/blobs` have been extracted from stock firmware and has "clean" state. + +## Specification + +```{eval-rst} ++------------------+------------------------------+ +| SoC | Intel TigerLake Halo | ++------------------+------------------------------+ +| PCH | Intel HM570 | ++------------------+------------------------------+ +| Super I/O | ITE IT8613E | ++------------------+------------------------------+ +| SPI | Winbond W25Q128FV 16MiB 3.3V | ++------------------+------------------------------+ +| NIC | Realtek RTL8111 | ++------------------+------------------------------+ +| Audio | Realtek ALC897 | ++------------------+------------------------------+ +``` + +[Erying Polestar G613 Pro]: https://www.erying.cc/products-detail/id-97.html +[microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/erying/tgl_matx_board.jpg b/Documentation/mainboard/erying/tgl_matx_board.jpg new file mode 100644 index 0000000..e0f2eed --- /dev/null +++ b/Documentation/mainboard/erying/tgl_matx_board.jpg Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 6178738..b016fce 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -94,6 +94,14 @@ QEMU POWER9 <emulation/qemu-power9.md> ```
+## Erying + +```{toctree} +:maxdepth: 1 + +Polestar G613 Pro <erying/tgl_matx.md> +``` + ## Facebook
```{toctree}
-
Alicja Michalska (Code Review)