Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/1
diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 7930793..65c6cab 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -78,7 +78,6 @@ _transfer_buffer = .; REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) - PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) @@ -86,6 +85,7 @@ FMAP_CACHE(., FMAP_SIZE) #if CONFIG(VBOOT) _etransfer_buffer = .; + PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 1:
"No Signed-off-by line in commit message"
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG@11 PS1, Line 11: transferred Could you please provide symbol addresses for before and after? nm on the resulting elfs from the build will provide you that. Grep for _epsp_sharedmem_dram:
$ nm coreboot-builds/GOOGLE_TREMBYLE/cbfs/fallback/bootblock.debug | grep _epsp_sharedmem_dram 02019000 T _epsp_sharedmem_dram
I see the following w/o your change in bootblock: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram
all x86 stages have the same addreses. However, are these addresses being relocated when being added to cbfs?
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 2:
I read the bug, and I see the macro was setting the location counter so this at least moves it to incorporate _etransfer buffer symbol and everything before it. I think the commit description could be improved based on the questions I was asking.
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/3
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below.
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/4
Josie Nordrum has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG@11 PS1, Line 11: transferred
Could you please provide symbol addresses for before and after? nm on the resulting elfs from the bu […]
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 4: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 4: Code-Review+2
(4 comments)
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 42: PSP_SHAREDMEM_SIZE VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 44: PSP_SHAREDMEM_SIZE VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 47: PSP_SHAREDMEM_SIZE VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 49: PSP_SHAREDMEM_SIZE This should be VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below.
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/5
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below.
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45045/6/src/soc/amd/picasso/memlayo... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/45045/6/src/soc/amd/picasso/memlayo... PS6, Line 47: * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE trailing whitespace
Josie Nordrum has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 42: PSP_SHAREDMEM_SIZE
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Done
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 44: PSP_SHAREDMEM_SIZE
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Done
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 47: PSP_SHAREDMEM_SIZE
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Done
https://review.coreboot.org/c/coreboot/+/45045/4/src/soc/amd/picasso/memlayo... PS4, Line 49: PSP_SHAREDMEM_SIZE
This should be VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Done
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45045
to look at the new patch set (#7).
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below.
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/7
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 7: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 7: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 7:
would like to land this early. thanks for the patience.
Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
soc/amd/picasso: Move DRAM end to after transfer buffer
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below.
BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer
AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram
BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum josienordrum@google.com Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 7930793..00cdde6 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -39,14 +39,14 @@ * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE * | Preram CBMEM console | * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | + * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 * | Transfer Info Structure | * +--------------------------------+ PSP_SHAREDMEM_BASE @@ -78,7 +78,6 @@ _transfer_buffer = .; REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) - PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) @@ -86,6 +85,7 @@ FMAP_CACHE(., FMAP_SIZE) #if CONFIG(VBOOT) _etransfer_buffer = .; + PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
-
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build bot (Jenkins) (Code Review)
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